• Title/Summary/Keyword: 동시 스케줄

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Dual Token Bucket based HCCA Scheduler for IEEE 802.11e (IEEE 802.11e WLAN 위한 이중 리키 버킷 기반 HCCA 스케줄러)

  • Lee, Dong-Yul;Lee, Chae-Woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.11B
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    • pp.1178-1190
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    • 2009
  • IEEE 802.11e proposed by IEEE 802.11 working group to guarantee QoS has contention based EDCA and contention free based HCCA. HCCA, a centralized polling based mechanism of 802.11e, needs a scheduling algorithm to allocate the network resource efficiently. The existing standard scheduler, however, is inefficient to support for QoS guarantee for real-time service having VBR traffic. To efficiently assign resource for VBR traffic, in this paper, we propose TXOP algorithm based on dual leaky bucket using average resource allocation and peak resource allocation. The minimum TXOP of each station is obtained by using statistical approach to maximize number of stations of which performance satisfy QoS target. Simulation results show that the proposed algorithm has much higher performance compared with reference scheduler in terms of throughput and delay.

Hardware Design of Bilateral Filter Based on Window Division (윈도우 분할 기반 양방향 필터의 하드웨어 설계)

  • Hyun, Yongho;Park, Taegeun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.12
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    • pp.1844-1850
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    • 2016
  • The bilateral filter can reduce the noise while preserving details computing the filtering output at each pixels as the average of neighboring pixels. In this paper, we propose a real-time system based on window division. Overall performance is increased due to the parallel architectures which computes five rows in the kernel window simultaneously but with pipelined scheduling. We consider the tradeoff between the filter performance and the hardware cost and the bit allocation has been determined by PSNR analysis. The proposed architecture is designed with verilogHDL and synthesized using Dongbu Hitek 110nm standard cell library. The proposed architecture shows 416Mpixels/s (397fps) of throughput at 416MHz of operating frequency with 132K gates.

A Recovery Mechanism for Server Failure in Database Systems based on Mobile computing Environments (이동 컴퓨팅 환경에 기반을 둔 데이터베이스 시스템에서 서버의 고장 회복 기법)

  • Jo, Jeong-Ran;Hwang, Bu-Hyeon
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.1
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    • pp.1-10
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    • 1999
  • A mobile computing environment is one that support user's mobility through the wireless communication technology. Users access the database and get results what they want by running mobile transactions. To run the mobile transaction correctly and to maintain the consistency I database, we need a concurrency control method to schedule transactions, a caching method to manage the cache, and a recovery method to construct a fault tolerant system. A mobile computing system is based on the existing distributed system, but we can't use recovery methods of the existing distributed system directly because of the user's mobility and the features of wireless media. So this paper presents a recovery mechanism to construct a fault tolerant mobile computing systems. Especially. we develop and analyze a recovery algorithm for server failure among types of failure which can arise in mobile computing environments.

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A Cryptoprocessor for AES-128/192/256 Rijndael Block Cipher Algorithm (AES-128/192/256 Rijndael 블록암호 알고리듬용 암호 프로세서)

  • 안하기;박광호;신경욱
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.05a
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    • pp.257-260
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    • 2002
  • This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm“Rijndael”. To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation the round transformation block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

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Multi-Cell Transmit Diversity Scheme for OFDMA Systems (OFDMA 시스템을 위한 다중 셀 전송 다양성 기법)

  • Seo, Bangwon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37A no.9
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    • pp.721-727
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    • 2012
  • Since a conventional multi-cell transmit diversity scheme depends on the feedback from the user for the channel gain information, its performance gets to severely degrade when the channel varies fast due to the high mobility of the user. Also, transmit power of the base station cannot be fully used in the conventional scheme because only one transmit antenna is used for data transmission. In this paper, we propose a multi-cell transmit diversity scheme appropriate for fast fading channel. In the proposed scheme, channel-independent precoding vector is applied over all transmit antennas and different precoding vectors are applied for neighboring subcarriers so that the received signal is avoided to experience deep fading over multiple neighboring subcarriers. Simulation results show that the proposed scheme has better detector output signal-to-noise ratio (SNR) and bit error rate (BER) performances than the conventional scheme.

An MHP based Data Service for Managing Viewer's Favorite Broadcasting Programs (MHP 기반의 시청자 선호 방송 프로그램 관리 데이터 서비스)

  • Ko, Kwang-Il
    • Journal of Digital Contents Society
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    • v.13 no.2
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    • pp.197-203
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    • 2012
  • Although the increase in number of the programs provides rich entertainment to viewers, it also has caused a negative of making it hard for viewers to find out their favorite programs. To address the problem, several researches have been performed mainly focusing on the technologies to analyze a viewer's TV watching-patterns and to recommend a program (or a channel) based on the analysis when a viewer changes channels. The researches, however, have the trouble of frequently failing to choose proper programs because, in the real-world broadcasting circumstance, the programs are re-broadcast over a number of the channels and a set of programs of a genre are usually playing in the overlapped times. To avoid the trouble, the data service, proposed in the paper, allows a viewer to book "explicitly" his/her favorite programs and provides a set of functions of listing up the booked program's broadcasting schedules and reserving viewing or recording the booked programs.

AES-128/192/256 Rijndael Cryptoprocessor with On-the-fly Key Scheduler (On-the-fly 키 스케줄러를 갖는 AED-128/192/256 Rijndael 암호 프로세서)

  • Ahn, Ha-Kee;Shin, Kyung-Wook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.11
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    • pp.33-43
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    • 2002
  • This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into a round transformation block, resulting that two consecutive round functions are simultaneously operated. For area-efficient and low-power implementation, the round transformation block is designed to share the hardware resources for encryption and decryption. An efficient on-the-fly key scheduler is devised to supports the three master-key lengths of 128-b/192-b/256-b, and it generates round keys in the first sub-pipeline stage of each round processing. The Verilog-HDL model of the cryptoprocessor was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}m$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

An Efficient Wrapper Design for SOC Testing (SOC 테스트를 위한 Wrapper 설계 기법)

  • Choi, Sun-Hwa;Kim, Moon-Joon;Chang, Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.3
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    • pp.65-70
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    • 2004
  • The SOC(System on Chip) testing has required the core re-use methodology and the efficiency of test method because of increase of its cost. The goal of SOC testing is to minimize the testing time, area overhead, and power consumption during testing. Prior research has concentrated on only one aspect of the test core wrapper design problem at a test time. Our research is concentrated on optimization of test time and area overhead for the core test wrapper, which is one of the important elements for SOC test architecture. In this paper, we propose an efficient wrapper design algorithm that improves on earlier approaches by also reducing the TAM(Test Access Mechanism) width required to achieve these lower testing times.

An Efficient Model and Algorithm to Allocate Rail Track Capacity Considering Line Plans (노선 계획을 고려한 철도 선로 용량 배분 최적화 모형 및 해법)

  • Park, Bum Hwan;Chung, Kwang Woo
    • Journal of the Korean Society for Railway
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    • v.17 no.6
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    • pp.466-473
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    • 2014
  • Recently, there is has been significant interest in the allocation systems of rail track capacities with considerations of the multiple train operating companies. The system indicates both a well-defined procedure and an algorithmic method to allocate the rail track capacities. Among them, this study considers the algorithmic method to derive the optimal timetable for the trains, which the companies propose together with their arrival and departure times at each station. However, most studies have focused on the adjustment of the departure and arrival times without conflicts, which could result in incompatible allocations with the line plan, which would result in an insufficient number of trains on each line to satisfy the demands. Our study presents a new optimization model and algorithm for the allocation problem in order to reflect the predetermined line plan. Furthermore, we provide the experimental results that were applied to the Korean high-speed railway network including the Suseo lines.

Design of YK2 Cipher Algorithm for Electronic Commerce Security (전자상거래 보안을 위한 YK2 암호 알고리즘 설계)

  • Kang, Young-Ku;Rhew, Sung-Yul
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.10
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    • pp.3138-3147
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    • 2000
  • EC(Electronic Commerce) which is cone the virtual space through Internet, has the advantage of time and space. On the contrary, it also has weak point like security probelm because anybody can easily access to the system due to open network attribute of Internet. Theretore, we need the solutions that protect the EC security problem for safe and useful EC activity. One of these solution is the implemonlation of a strong cipher algorithm. YK2(YoungKu Kang) cipher algorithm proposed in this paper is advantage for the EC security and it overcomes the limit of the current 6/1 bits block cipher algorithm using 128 bits key length for input, output, encryption key and 32 rounds. Moreover, it is degigned for the increase of time complexity and probability calculation by adapting more complex design for key scheduling regarded as one of the important element effected to enciyption.

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