• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.6
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• pp.1214-1219
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• 2009

Many studies are being applied for various parts of USN (Ubiquitous Sensor Network) technology. The world's large retail stores and warehouses that apply logistic management are also studied. With this, USN technology is increasing in its utilization. However, to handle and process real-time data will never be never easy if these huge warehouses are using too many sensors, and real-time data correction is almost impossible. Software implementation and high-speed hardware are insufficient to solve these complex problems. To solve this problem, a key solution is to implement high-speed software. Hence, this paper suggests a USN logistics management system that applies pipelining techniques for efficiency in real-time data correction and reduces errors of generated values.

• Journal of the Korea Society of Computer and Information
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• v.7 no.3
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• pp.135-142
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• 2002

In this paper, we proposed the new structure of the Rake Finger using Walsh Switch, the shared accumulator and the pipeline FWHT algorithm for reducing the signal processing complexity resulting from the increase of the number of data correlators. The number of computational operation in the proposed data correlators is 160 additions when the number of walsh code channels is 4. As a result, it is reduced about 3.2 times other than the number of computational operation of the conventional ones. Also, the result shows that the data processing time of the proposed Rake Finger architecture is 90,496〔ns〕 and the conventional ones is 110,696〔ns〕. It is 18.3% faster than the data processing time of the conventional Rake Finger architecture.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.648-650
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• 2000

라우터의 기본적인 목적은 안정적으로 다량의 데이터를 전송하는 것이다. 현재 e양한 메시지를 효과적으로 처리하기 위한 여러 혼합형 라우터가 개발되고 있다. 이는 단순히 한가지 방식만 고수하는 것이 아니라 기존의 여러 기법을 혼합된 방식을 적용하는 것이다. 이러한 혼합형 기법은 기존의 단일 방식의 단점을 보완할 수 있어야 하며, 그에 따른 오버헤드를 감수할 수 있어야 한다. 이러한 목적으로 웜홀 스위칭(wormhole switching)과 파이프라인드 서킷 스위칭(Pipelined Circuit Switching)을 동시에 구현하기 위해 혼합형 라우터 구조가 제안되었다. 이 라우터는 두 스위칭 기법을 동시에 지원하여 다양한 메시지를 효과적으로 처리할 수 있는 특성이 있다. 그러나 이 구조는 각 스위칭 방식에 해당하는 내부 연결망을 독립적으로 구성함으로써 입력으로 들어오는 스위칭 비율이 불균형일 때 내부 자원을 효율적으로 사용할 수 없는 단점이 있다. 따라서 본 논문에서는 라우터의 내부 연결망을 공유하여 사용하는 새로운 혼합형 라우터를 제안하였다. 제안한 구조는 웜홀과 파이프라인드 서킷 스위칭을 지원하는 라우터로, 메시지를 전송할 때 내부 연결망을 서로 공유함으로써, 입력 메시지의 비율이 불균형할 때 효과적으로 자원을 이용할 수 있게 하였다. 시뮬레이션을 통하여 기존의 혼합형 라우터를 사용하는 것보다 더 높은 성능을 보인다는 것을 증명하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.29-38
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• 2009

In this paper, a high performance pipelined computing design of parallel multiplier-temporal buffer-parallel accumulator is present for the convolution-based non-cascaded architecture aiming at the real time Discrete Wavelet Transform(DWT) processing. The convolved multiplication of DWT would be reduced upto 1/4 by utilizing the filter coefficients symmetry and the up/down sampling; and it could be dealt with 3-5 times faster computation by LUT-based DA multiplication of multiple filter coefficients parallelized for product terms with an image data. Further, the reutilization of computed product terms could be achieved by storing in the temporal buffer, which yields the saving of computation as well as dynamic power by 50%. The convolved product terms of image data and filter coefficients are realigned and stored in the temporal buffer for the accumulated addition. Then, the buffer management of parallel aligned storage is carried out for the high speed sequential retrieval of parallel accumulations. The convolved computation is pipelined with parallel multiplier-temporal buffer-parallel accumulation in which the parallelization of temporal buffer and accumulator is optimize, with respect to the performance of parallel DA multiplier, to improve the pipelining performance. The proposed architecture is back-end designed with 0.18um library, which verifies the 30fps throughput of SVGA(800$\times$600) images at 90MHz.

• The KIPS Transactions:PartB
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• v.9B no.6
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• pp.715-726
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• 2002

In this paper, we construct real-time moving picture encoder based on fractal theory by using general purpose digital signal processors. The constructed encoder is implemented using two fixed-point general DSPs (ADSP2181) and performs image encoding by three stage pipeline structure. In the first pipeline stage, the image grabber acquires image data from NTSC standard image signals and stores digital image into frame memory. In the second stage, the main controller encode image dada using fractal algorithm. The last stage, output controller perform Huffman coding and result the coded data via RS422 port. The performance tests of the constructed encoder shows over 10 frames/sec encoding speed for QCIF data when all the frames are encoded. When we encode the images using the interframe and redundency based on the proposed algorithms, encoding speed increased over 30 frames/sec in average.

• The Journal of Bigdata
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• v.8 no.1
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• pp.61-71
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• 2023

With the development of data-driven decision-making and sophisticated big data processing technique, there is a growing demand for information on how to process data. However, recent studies with data preprocessing mentioned only as a means to achieve a result. Therefore, in this study, we aimed to write in detail about the data processing pipeline, include preprocessing data. In particular, we shares the context and domain knowledge to aid fluent understand of the research.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.155-164
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• 2015

This paper describes a design and implementation of CABAC decoder, which would handle HEVC syntax elements in adaptively pipelined-parallel computation manner. Even though CABAC offers the high compression rate, it is limited in decoding performance due to context-based sequential computation, and strong data dependency between context models, as well as decoding procedure bin by bin. In order to enhance the decoding computation of HEVC CABAC, the flag-type syntax elements are adaptively pipelined by precomputing consecutive flag-type ones; and multi-bin syntax elements are decoded by processing bins in parallel up to three. Further, in order to accelerate Binary Arithmetic Decoder by reducing the critical path delay, the update and renormalization of context modeling are precomputed parallel for the cases of LPS as well as MPS, and then the context modeling renewal is selected by the precedent decoding result. It is simulated that the new HEVC CABAC architecture could achieve the max. performance of 1.01 bins/cycle, which is two times faster with respect to the conventional approach. In ASIC design with 65nm library, the CABAC architecture would handle 224 Mbins/sec, which could decode QFHD HEVC video data in real time.

• Journal of IKEEE
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• v.13 no.4
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• pp.110-115
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• 2009

The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation. The quarter-pixel interpolation is achieved using 6-tap horizontal or vertical FIR filters for luminance data and bilinear FIR filters for chroma data. We propose the architecture for interpolation of luminance and chroma data in H.264 decoders. It is composed of dual-channel pipelined processing elements and can interpolate integer-, half- and quarter-pixel data. The number of the processing cycles is different depending on the position. The processing elements are composed of adders and shifters to reduce the complexity while the accuracy of the pixel data are maintained. We design interpolators for luminance and chroma data using Verilog-HDL and verify the function and performance by implementing using an FPGA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.407-413
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• 2015

In this paper, a DFPA(decimal floating-point adder) designed a pipeline structure that uses a LZA(leading zero anticipator) to reduce critical route to shorten delay to improve the speed of operation processing. The evaluation and verification of performance of proposed DFPA applied the Flowrian tool with simulation and Cyclone III FPGA was set as the target on the Quartus II tool for the synthesis. The proposed method compared and verified to proposed the other method using same input data. As a result, the performance of proposed method is improved 11.2% and 5.9% more than L.K.Wang's method and etc.. Also, it is confirmed that improvement of operation processing speed and reduction of the number of delay elements on critical path.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1709-1716
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• 2007

In this paper, ADC with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB$ and $0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.