• Journal of the Korea Society of Computer and Information
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• v.6 no.4
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• pp.94-99
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• 2001

Recently a lot of informations is interchanged among many users through the network such as Internet. In this situation. multimedia data transfer has some problems. that are jitter, the difference of delay in arriving packets, and loss of data due to the various delay between sender and receiver. The arriving data packets are not synchronized because of those problems. Especially, an efficient method is needed to revise the sudden large changes of the delay, called spike-like delay. which is occured in explosive growth of networking. We propose efficient synchronization algorithm which controls synchronization interval and adjusts to sudden changes in networks. The algorithm, a receiver-driven adaptive synchronization method, is to synchronize the arriving data packets against spike-like delay and decrease the loss of them. In addition, another method is proposed in this paper. The method uses the probabilistic features of delay distribution appearing in general network. It is evaluated for the loss of data packets and the delay times.

• Journal of IKEEE
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• v.17 no.2
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• pp.168-175
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• 2013

The delay times due to the propagating of data on PCB depend on the shape and length of interconnection lines when memory controllers and high speed memories are soldered on the PCB. The dependency on the placement and routing on the PCB requires redesign of I/O logic or reconfiguration of the memory controller after the delay time is measured if the controller is programmable. In this paper, we propose architecture of configuring logic for the delay time estimation by writing and reading test patterns while initializing the memories. The configuration logic writes test patterns to the memory and reads them by changing timing until the correct patterns are read. The timing information is stored and the configuration logic configures the memory controller at the end of initialization. The proposed method enables easy design of systems using PCB by solving the problem of the mismatching caused by the variation of placement and routing of components including memories and memory controllers. The proposed method can be applied to high speed SRAM, DRAM, and flash memory.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.5
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• pp.115-121
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• 2009

In this paper, we propose an algorithm that reduces channel change delay time in the P2P based IPTV system. Channel change delay time is considered to be one of the most important performance measures in IPTV system. Proposed algorithm presents a method to reduce the channel change delay time effectively. The algorithm eliminates the first channel change delay time and reduces delay time on a continuous channel surfing. We will show the mathematical models to evaluate the performance of proposed scheme with respect to the channel change delay time.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.1
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• pp.17-27
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• 2012

Broadcast-based data dissemination has become a widely accepted approach of communication in the mobile computing environment. However, with a large set of data items, the expected delay of receiving a desired data increases due to the sequential nature of the broadcast channel. This paper explores the issue of designing proper data allocation on multiple broadcast channels to reduce this wait time, and proposes a new data allocation scheme named near optimal data allocation(NODA). The proposed scheme first partitions all data items in K group based on the theoretical lower-bound of the average expected delay to determine data items which each broadcast channel has to broadcast. Then, NODA further partitions each group of data items in B groups using extended dynamic programming algorithm to broadcast data items allocated on the same broadcast channel in different frequencies. The proposed scheme is capable of minimizing the average expected delay time since it can broadcast data items allocated on the same channel reflecting their popularities.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2021.11a
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• pp.172-173
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• 2021

자율운항선박의 원격제어에서 제어지연이 발생하면 선박은 충돌위험에 처하게 됨으로 이에 대한 해결방안 필요하다. 연구 목적은 자율운항선박의 원격제어에서 제어지연이 선박충돌에 미치는 영향을 조사하기 위함이다. 연구 방법은, 선박의 터닝서클을 시뮬레이션을 통해서 관측하고, 이 데이터를 이용하여 제어지연에 의한 영향을 분석하였다. 이를 위하여 제어지연(시간)에 따른 선박조종 시뮬레이션의 선회권 측정 데이터를 이용하였다. 연구 결과, 제어지연에 의해서 본선 도메인 침공당하는 방위와 최소거리 분석 가능함을 알았다.

• The KIPS Transactions:PartC
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• v.17C no.6
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• pp.459-464
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• 2010

Due to the application-specific nature of wireless sensor networks, the sensitivity to such a requirement as data reporting latency may vary depending on the type of applications, thus requiring application-specific algorithm and protocol design paradigms which help us to maximize energy conservation and thus the network lifetime. In this paper, we implement and evaluate a novel delay-adaptive sensor scheduling scheme for energy-saving data gathering which is based on a two phase clustering (TPC), in wireless sensor networks. The TPC is implemented on sensor Mote hardwares. With the help of TPC implemented, sensors selectively use direct links for control and forwarding time critical sensed data and relay links for data forwarding based on the user delay constraints given. Implementation study shows that TPC helps the sensors to increase a significant amount of energy while collecting sensed data from sensors in a real environment.

• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.7-10
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• 2018

통합 메모리는 CPU 메모리와 GPU 메모리 간의 데이터 통신을 개발자에게 투명하게 내재적으로 수행하는 소프트웨어 런타임 환경으로 개발자에게 CPU 메모리와 GPU 메모리가 통합된 하나의 메모리로 보이게 해준다. 통합 메모리는 장점에도 불구하고 아직 널리 사용되지 못하고 있는데 그 이유는 내재적으로 수행되는 데이터 통신의 오버헤드가 큰 것으로 알려져 있기 때문이다. 하지만 이 데이터 통신이 구체적으로 어떻게 이루어지고 오버헤드는 어떻게 발생하는지 분석한 연구는 아직 존재하지 않는다. 우리는 NVIDIA 사의 최신 GPU 마이크로아키텍처 중 하나인 파스칼을 사용하는 GPU를 대상으로 하여, 통합 메모리를 사용할 시 데이터 통신이 이루어지는 조건과 GPU 응용의 수행시간에 데이터 통신이 끼치는 영향을 실험을 통해 분석한다. 실험 결과 통합 메모리의 오버헤드는 두 가지 원인 때문에 발생한다. 첫째, 통합 메모리를 사용하면 CPU 또는 GPU가 데이터에 접근할 때마다 이 데이터는 CPU 또는 GPU 메모리로 옮겨지고 옮겨진 데이터는 제거된다. 따라서 재사용할 데이터도 제거되어 추가적인 데이터 통신이 발생하고, 이 데이터 통신의 지연시간은 GPU 응용의 수행시간에 더해진다. 둘째, 통합 메모리를 사용하면 데이터 통신과 커널들이 서로 다른 스트림에 할당되어도 동시에 수행되지 못한다. 따라서 GPU 응용의 수행시간은 동시에 수행되던 데이터 통신과 커널의 수행시간만큼 증가한다.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.3
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• pp.493-498
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• 2017

Recently, traffic data is analyzed for efficiency of bus operation, D2D(: Door to Door) service, and self-driving of public transportation. However, various studies have been carried out to predict the delay time of public transportation, especially buses, but the research to date has been insufficient due to limitations of simple analysis and data acquisition. In this study, delay time estimation is performed by collecting and processing data such as day of the week, weather, and time of day based on bus operation information. The proposed method in this paper can be applied to autonomous public transport and public traffic control system by improving the accuracy by adding variables in the future.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10e
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• pp.22-24
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• 2002

이동 IP 망에서 이동 IP의 삼각 라우팅 문제를 해결한 최적경로 IP 라우팅 기법은이동 IPv6망에서의 이동성을 지원하는 기본 동작으로 되어있다. 본 논문에서는 이동 IP망의최적 경로 기법을 NBMA망에서의 NHRP를 이용한 단거리 터널설정 기법을 적용하여 그 성능을 평가하였다. 패킷 전달지연 시간 측면에서 기존 IP 라우팅 기법과 최적 경로에서의단거리 터널링 기법을 상호 비교하기 위하여 수학적 분석 및 모의실험을 수행하였다. 최적경로의 단거리 터널링 기법은 기존 IP 라우팅 방식보다 초기 데이터의 경우 종단간 전달 지연시간이 클 수 있으나 이후 패킷부터는 종단간 데이터 전달 지연시간이 대폭 개선됨을 확인하였다.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.9
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• pp.461-468
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• 2001

Though shared virtual memory (SVM) system promise low cost solutions for high performance computing they suffer from long memory latencies. These latencies are usually caused by repetitive invalidations on shared data. Since shared data are accessed through synchronization and the patterns by which threads synchronizes are repetitive, a prefetching scheme bases on such repetitiveness would reduce memory latencies. Based on this observation, we propose a prefetching technique which predicts future access behavior by analyzing access history per synchronization variable. Our technique was evaluated on an 8-node SVM system using the SPLASH-2 benchmark. The results show the our technique could achieve 34%~45% reduction in memory access latencies.