• Journal of Internet Computing and Services
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• v.7 no.3
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• pp.107-118
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• 2006

Recently, network infra grows rapidly and the digital image compression technique have made remarkable progress, and therefore the demand of the real-time image surveillance system which uses a network camera server is increasing. Network Camera Server has emerged as an attractive alternative to the CCTV for the real-time image surveillance. From this reason, the demand regarding the development of the real-time image surveillance system which uses a network camera server is increasing as well. In this paper, we will provide a model for JPEG Streamer which is used in real-time image surveillance system. And we will design and implement this model. For the stability and efficiency of the JPEG Streamer, we'll use the thread pool and shared memory. We will also introduce the concept of double buffering for increasing the quality of real-time image, Using the JPEG Streamer, a raising of the productivity, reliability and stability will be able to secure to development of real-time image surveillance system.

• Journal of KIISE:Computing Practices and Letters
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• v.10 no.6
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• pp.499-506
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• 2004

The copper foil surface inspection system is necessary for the factory automation and product quality. The developed system is composed of the high speed line scan camera, the image capture board and the processing computer. For the system resource utilization and real-time processing, multi-threaded architecture is introduced. There are one image capture thread, 2 or more defect detection threads, and one defect communication thread. To process the high-speed input image data, the I/O overlap is used through the double buffering. The defect is first detected by the predetermined threshold. To cope with the light irregularity, the compensation process is applied. After defect detection, defect type is classified with the defect width, eigenvalue ratio of the defect covariance matrix and gray level of defect. In experiment, for high-speed input image data, real-time processing is possible with multi -threaded architecture, and the 89.4% of the total 141 defects correctly classified.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1914-1919
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• 2021

With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.