• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.6
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• pp.561-568
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• 2003

There arc two ways in the output voltage control method in PWM inverters. One Is double loop voltage control composed of inner current control loop and outer voltage control loop.'rho other is single loop voltage control method composed of voltage control loop only. It's characteristics shows lower performance in case of high output impedance than double loop voltage control. However, in case of low output impedance, it shows good control performance in all load ranges than double loop voltage control. In this paper, the rule and the gain of single loop voltage control have been developed analytically and these were verified through computer simulation and experiment.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.542-543
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• 2012

본 논문에서는 저항성 수하제어 방식과 단일루프 강인 전압 제어기를 적용하여 단상 UPS 인버터의 비통신선 방식 5-병렬 운전 결과를 기술한다. 단일 루프 강인 전압 제어기를 이용해 단상 3kVA UPS 인버터 5대로 병렬운전 환경을 구축하였고, 저항성 주파수-전압 강하 방식의 수하 제어를 이용하여 저항 부하와 선형 부하에 대한 전력분담 특성을 PSIM 시뮬레이션을 통하여 확인하였다.

• Proceedings of the KIPE Conference
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• 2011.11a
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• pp.203-204
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• 2011

단일 루프 강인 전압 제어기를 이용한 단상 3kVA UPS 인버터의 비통신선 방식 병렬 운전 결과를 기술한다. 단상 UPS 인버터 2대로 병렬운전 실험 환경을 구축하였고, 주파수-전압 강하 방식의 수하 제어를 이용하여 저항 부하, 비선형 부하에 대한 전력분담을 실험을 통하여 확인하였다.

• ICROS
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• v.17 no.4
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• pp.46-50
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• 2011

다변수 입출력 제어시스템에서 제어기를 설계하기 위해서는 단일 입출력 시스템에서와 마찬가지로 저주파수영역에서는 루프전달행렬의 크기가 작은 것이 요구되고, 측정잡음 및 플랜트의 불확실성이 존재하는 고주파수 영역에서는 루프전달행렬의 크기가 작게 되도록하여, 잡음의 영향이 출력에 적게 나타나고, 제어기가 포화되지 않도록 하며, 설계된 제어기가 플랜트 모델의 불확실성을 극복할 수 있게 하는 것이 필요하다. 본 원고에서는 각 전달 행렬들의 특이치의 최대 및 최소값들을 이용하여 다변수 제어기가 갖추어야 할 조건들을 정리하였다.

• 한국태양에너지학회:학술대회논문집
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• 2012.03a
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• pp.153-159
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• 2012

In photovoltaic system, the characteristic of photovoltaic module such as open circuit voltage and short circuit current will be changed because of cell temperature and solar radiation. Therefore, a boost converter of the PV system connects between the output of photovoltaic system and DC link capacitor of grid connected inverter as controlling duty ratio for maximum power point tracking(MPPT). This paper shows the dynamic characteristic of the boost converter by comparing single-loop control algorithm and two-loop control algorithm using both analog and digital control. The proposed both compensation method has been verified with computer simulation and simulation results obtained demonstrate the validity of the proposed control schemes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.7
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• pp.17-22
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• 2012

A novel Clock Generator with jitter suppressed delay-locked loop (DLL) has been proposed to generate highly accurate output signals. The proposed Clock Generator has a VCDL which can suppress its jitter by generating control signals proportional to phase differences among delay stages. It has been designed to generate 1GHz output at 100MHz input with 1.8V $0.18{\mu}m$ CMOS process. The simulation result demonstrates a 3.24ps of peak-to-peak jitter.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.313-314
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• 2015

본 논문은 3상 4선식 인버터를 이용하여 임의의 전압 파형을 발생하기 위한 우수한 성능의 폐루프 전압 제어기를 제안하고 제어 이득 설정 방법을 제시한다. 먼저, 임의 파형 발생기에 사용된 3상 4선식 인버터 및 LC 필터 회로 구조를 분석하고, 이를 기반으로 한 전압 제어기 구조를 제안한다. 제안된 전압 제어기는 폐루프 형태의 PI 전압 제어기를 사용하고, 과도 특성 개선 및 부하 전류로 인한 전압 왜곡 방지를 위해 인버터 전류 및 부하 전류 정보를 전향 보상에 사용한다. 실험을 통해 전압 지령에 대한 응답 특성이 향상되는 것을 확인할 수 있다.

• The KIPS Transactions:PartD
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• v.15D no.2
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• pp.197-206
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• 2008

The CTOC framework was implemented to efficiently perform analysis and optimization of the Java bytecode that is often being used lately. In order to analyze and optimize the bytecode from the CTOC, the eCFG was first generated. Due to the bytecode characteristics of difficult analysis, the existing bytecode was expanded to be suitable for control flow analysis, and the control flow graph was drawn. We called eCFG(extended Control Flow Graph). Furthermore, the eCFG was converted into the SSA Form for a static analysis. Many loops were found in the conversion program. The previous CTOC performed conversion directly into the SSA Form without processing the loops. However, processing the loops prior to the SSA Form conversion allows more efficient generation of the SSA Form. This paper examines the process of finding the loops prior to converting the eCFG into the SSA Form in order to efficiently process the loops, and exhibits the procedures for generating the loop tree.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1552-1558
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• 2011

In this paper, a dual-loop Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a low power consuming voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF which occupies a large area. The proposed dual-loop P DLL can have a small gain VCDL by controlling the magnitude of capacitor and charge pump current on the loop of VCDL. The proposed dual-loop P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by Hspice simulation.

• Journal of the Korean Solar Energy Society
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• v.32 no.spc3
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• pp.245-254
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• 2012

In photovoltaic system, the characteristics of photovoltaic module such as open circuit voltage and short circuit current will be changed because of cell temperature and solar radiation. Therefore, the boost converter of a PV system connects between the output of photovoltaic system and DC link capacitor of grid connected inverter as controlling duty ratio for maximum power point tracking(MPPT). This paper shows the dynamic characteristics of the boost converter by comparing single-loop and two-loop control algorithm using both analog and digital control. Both proposed compensation methods have been verified with computer simulation to demonstrate the validity of the proposed control schemes.