• Journal of Internet of Things and Convergence
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• v.9 no.3
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• pp.81-86
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• 2023

SSD (solid state disk), which is flash memory-based storage device, has the advantages of high density and fast data processing. Therefore, it is being utilized as a storage device for high-capacity data storage systems that manage rapidly increasing big data. However, flash memory, a storage media, has a physical limitation that when the write/erase operation is repeated more than a certain number of times, the cells are worn out and can no longer be used. In this paper, we propose a method for converting defective multi-bit cells into single-bit cells to reduce the defect rate of flash memory and extend its lifetime. The proposed idea distinguishes the defects and treatment methods of multi-bit cells and single-bit cells, which have different physical characteristics but are treated as the same defect, and converts the expected defective multi-bit cells into single-bit cells to improve the defect rate and extend the overall lifetime. Finally, we demonstrate the effectiveness of our proposed idea by measuring the increased lifetime of SSD through simulations.

• Journal of Internet of Things and Convergence
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• v.9 no.4
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• pp.9-14
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• 2023

Recently, resource optimization research has been actively conducted in enterprises and data centers to manage the rapid growth of big data. In particular, thin provisioning, which allocates a large number of resources compared to fixedly allocated storage resources, has the effect of reducing initial costs, but as the number of resources actually used increases, the cost effectiveness decreases and the management cost for allocating resources increases. In this paper, we propose a technique that divides the physical blocks of flash memory into single-bit cells and multi-bit cells, formats them with a hybrid technique, and manages them by dividing frequently used hot data and infrequently used cold data. The proposed technique has the advantage that the physical and allocated resources are the same, such as thick provisioning, and can be used without additional cost increase, and the underutilized resources can be managed in multi-bit cell blocks, such as thin provisioning, which can allocate more resources than typical storage devices. Finally, we estimated the resource optimization effectiveness of the proposed technique through experiments based on simulations.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.10-17
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• 1999

In this paper, CMOS IADC(Current-mode Analog-to-Digital Converter) which consists of only CMOS transistors is proposed. Each stages is made up 1.5-bit bit cells composed of CSH(Current-mode Sample-and-Hold) and CCMP(Current Comparator). The differential CSH which designed to eliminate CFT(Clock Feedthrough), to meet at least 9-bit resolution, is placed at the front-end of each bit cells, and each stages of bit cell ADSC (Analog-to-Digital Subconverter) is made up two latch CCMPs. With the HYUNDAI TEX>$0.65\mu\textrm{m}$ CMOS parameter, the ACAD simulation results show that the proposed IADC can be operated with 47 dB of SINAD(Signal to Noise- Plus-Distortion), 50dB(8-bit) of SNR(Signal-to-Noise) and 37.7 mW of power consumption for input signal of 100 KHz at 20 Ms/s.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.10-21
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• 1999

This paper describes a 12bit CMOS current cell matrix D/A converter which shows a conversion rate of 65MHz and a power supply of 3.3V. Designed D/A converter utilizes current cell matrix structure with good monotonicity characteristic and fast settling time, and it is implemented by using the tree structure bias circuit, the symmetrical routing method with ground line and the cascode current switch to reduce the errors of the conventional D/A converter caused by a threshold voltage mismatch of current cells and a voltage drop of the ground line. The designed D/A converter was implemented with a $0.6{\mu}m$ CMOS n-well technology. The measured data shows a settling time of 20ns, a conversion rate of 50 MHz and a power dissipation of 35.6mW with a single power supply of 3.3V. The experimental SNR, DNL, and INL of the D/A converter is measured to be 55dB, ${\pm}0.5LSB$, and ${\pm}2LSB$, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1088-1097
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• 1999

In this paper we describe our investigation en ATM CLR(Cell Loss Rate) in the wireless ATM Networks, which consist of wireless access nodes and wireless links. A wireless access node is modelled as the ND/D/1queue. A wireless channel is modelled as channel with single and burst error characteristics, and it can be seen that the CLR degrades on a link with burst errors than on a link with single error. Because wireless channel can be approximated as the Rayleigh or Rician fading channel and wireless communication systems are power limited, it is customary that the CLR degrades on a link with burst errors than on a link with single error. So error control method should be used to improve performance degradation caused by burst errors. We consider the forward error correction(FEC) as error control scheme for CBR traffics to improve performance degradation caused by burst errors, and analyze performance of concatenated FEC scheme through the use of CLR.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7B
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• pp.1289-1295
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• 1999

본 논문에서는 스위치의 운용 알고리즘에 따라 시뮬레이션 프로그램을 이용하여 입/출력 버퍼의 셀 손실율을 측정하였다. 그 결과 셀 손실에 영향을 주는 요소로서, 셀 도착 간격 시간(k(a))과 SPEEDUP FACTOR(SF) en 가지 요소에 따라 셀손실을 평가할 수 있음을 알 수 있었다. 셀 도착 간격 시간 혹은 주기성은 비트가 셀로 모이는데 걸리는 시간을 의미하며 스위치 속도 SF는 임의의 한 슬롯내에서 한 입력단에서 출력단으로 서비스 가능한 셀의 수를 나타내고 있다. 시뮬레이션의 결과에서 보면 입력 버퍼에서는 주지성에 따라, 출력 버퍼에서는 SF의 크기에 따라 셀손실율이 커진다는 사실을 알 수 있었다. 따라서 보다 정확한 고속 스위칭 향상을 위해서는 입/출력 버퍼의 크기 결정이 중요하다. 본 논문의 시뮬레이션 결과에서는 입력 버퍼가 100x셀 일 때 출력 버퍼가 40x셀 정도의 크기가 적합하다는 것을 얻어내었다. 물론 입/출력 버퍼를 크게 한다면 셀 손실이 작아지지만, 하드웨어를 구성하는데 문제점이 발생될 것이기 때문이다. 그리고 본 논문 결과치중 셀 도착 분포 상황은 변동계수 모델링 성정에 따라 SF가 처리하는 서비스의 셀 도착 분포에 의 \ulcorner달라지지만, 변동계수가 전혀 없는 이상적인 경우(CV=1)를 제외한 경우의 SF값을 만족한다고 하겠다. 끝으로 입/출력 버퍼를 가진 스위치 구조는 단지 출력 버퍼를 갖는 스위치 보다 지연이 크지만, VLSI의 발달로 셀의 처리 속도가 증가하므로 더 많은 장점을 갖게 될 것이다.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.490-501
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• 1994

In this study the problems of cell marking method used in the field of ATM network traffic control are presented. Also an extended cell marking method considering the user level priority is proposed. The conventional traffic monitoring schemes set the CLP bit of a cell to 1 only under the circumstance of the violation of traffic contract. It causes that the number of low level cells increases and the levels of cells are lowered regardless of the user level priority. The three level priority control method combining FCI bit with CLP bit has also been proposed. It divides CLP=0 cells into two levels. Consequently, the proposed method preserves more cells in high level than the conventional one and the real loss of high level cells can be reduced. The performance of the proposed scheme has also been analyzed by the PBS(partial buffer sharing) with two thresholds for the proposed three levels. The result shows that the PBS with two thresholds can give more efficient control than the scheme with no priority, or the PBS with one threshold.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.18-24
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• 2012

This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.163-165
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• 2018

GF(p)상 타원곡선 암호(ECC)와 RSA를 단일 하드웨어로 통합하여 구현한 공개키 암호 프로세서를 설계하였다. 설계된 EC-RSA 공개키 암호 프로세서는 NIST 표준에 정의된 소수체 상의 224-비트 타원 곡선 P-224와 2048-비트 키 길이의 RSA를 지원한다. ECC와 RSA가 갖는 연산의 공통점을 기반으로 워드기반 몽고메리 곱셈기와 메모리 블록을 효율적으로 결합하여 최적화된 데이터 패스 구조를 적용하였다. EC-RSA 공개키 암호 프로세서는 Modelsim을 이용한 기능검증을 통하여 정상동작을 확인하였으며, $0.18{\mu}m$ CMOS 셀 라이브러리로 합성한 결과 11,779 GEs와 14-Kbit RAM의 경량 하드웨어로 구현되었다. EC-RSA 공개키 암호 프로세서는 최대 동작주파수 133 MHz이며, ECC 연산에는 867,746 클록주기가 소요되며, RSA 복호화 연산에는 26,149,013 클록주기가 소요된다.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.694-696
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• 2004

본 논문에서는 32$\times$32비트 곱셈 연산의 하위 32비트 결과를 한 클록 주기에 얻기 위한, 130MHz 파이프라인용 SIMD형 2단 곱셈 누산기를 설계하였다. 이 과정에서, Booth 부호기의 부분곱의 생성에 소요되는 지연을 줄이면서 부호가 있는 수의 연산을 수행할 수 있는 Booth 부호기를 설계하였다. 생성된 부분곱을 SIMD 명령어에 따라 크기가 선택된 Wallace Tree로 합산하고, 32$\times$32비트 곱셈 연산의 하위 32비트 결과를 제외한 모든 결과들은 두 번째 파이프라인 단에서 얻어지도록 하였다 현재 설계된 SIMD형 곱셈 누산기는 삼성 0.18$\mu\textrm{m}$ 표준 셀로 합성할 때, 1.65V, +1$25^{\circ}C$에서 약 7.61㎱의 임계 경로 지연을 갖는다