• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.8
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• pp.79-85
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• 2004

In this paper, the RF-ID system for ubiquitous tagging applications has been designed, fabricated and analysed. The RF-ID System consists of passive RF-ID Tag and Reader. The passive RF-ID tag consists of rectifier using zero-bias schottky diode which converts RF power into DC power, ID chip, ASK modulator using bipolar transistor and slot loop antenna. We suggest an ASK undulation method using a bipolar transistor to compensate the disadvantage of the conventional PIN diode, which needs large current Also, the slot loop antenna with wider bandwidth than that of the conventional patch antenna is suggested The RF-ID reader consist of patch array antenna, Tx/Rx part and ASK demodulator. We have designed the RF-ID System using EM and circuit simulation tools. According to the measured results, The power level of modulation signal at 1 m from passive RF-ID Tag is -46.76 dBm and frequency of it is 57.2 KHz. The transmitting power of RF-ID reader was 500 mW

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.31-39
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• 2009

This paper presents the single supply power line communication(PLC) SoC ASIC with built-in analog frond-end circuit. To achieve the low power consumption along with low chip cost, this PLC SoC ASIC employs fully CMOS analog front-end(AFE) and several built-in Regulators(LDOs) powering for Core logic, ADC, DAC and IP Pad driver. The AFE includes RX of pre-amplifier, Programmable gain amplifier and 10 bit ADC and TX of 10bit Digital Analog Converter and Line driver. This PLC Soc was implemented with 0.18um 1 Poly 5 Metal CMOS process. The single power supply of 3.3V is required for the internal LDOs. The total power consumption is below 30mA at standby and 300mA at active which meets the eco-design requirement. The chips size is $3.686\;{\times}\;2.633\;mm^2$.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.12
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• pp.1671-1674
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• 2014

This paper presents a frequency-dependent cell impedance analysis chip for use in cancer and normal cell discrimination. The previous cell impedance analysis chips for flowing cells cannot allow enough time for cell-to-electrode contact to monitor frequency-dependent impedance response. Another type of the previous cell impedance analysis chips for the cells clamped by membranes need complex sample control for making stable cell-to-electrode contact. We present a new impedance analysis chip using the microchamber array, on which a PDMS cover is placed to make stable cell-to-electrode contact for the individual cell trapped in each microchamber; thus achieving frequency-dependent single-cell impedance analysis without complex sample control. Compared to the normal cells, the magnitude of NHBE cells is $60.07{\sim}97.41k{\Omega}$ higher than A549 cells in the frequency range of 95.6 kHz~2MHz and the phase of NHBE is $3.96^{\circ}{\sim}20.8^{\circ}$ higher than A549 cells in the frequency range of 4.37 kHz~2MHz, respectively. It is demonstrated experimentally that the impedance analysis chip performs frequency-dependent cell impedance analysis by making stable cell-to-electrode contact with simple sample control; thereby applicable to the normal cell and cancer cell discrimination.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.5
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• pp.542-546
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• 2008

Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local memories and the shared memory for both processors. In order to maintain memory consistency from simultaneous accesses of both ports, every access to the shared memory should be protected by a synchronization mechanism, which can result in substantial access latency. We propose two optimization techniques by exploiting the communication patterns of target applications: lock-priority scheme and static-copy scheme. Further, by dividing the shared bank into multiple blocks, we allow simultaneous accesses to different blocks thus achieve considerable performance gain. Experiments on a virtual prototyping system show a promising result - we could achieve about 20-50% performance gain compared to the base DPSDRAM architecture.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.587-597
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• 2005

Flash memory based embedded computing systems are becoming increasingly prevalent.These systems typically have to provide an instant start-up time. However, we observe that mounting a file system toy flash memory takes 1 to 25 seconds mainly depending on the flash capacity. Since the flash chip capacity is doubled in every year, this mounting time will soon become the most dominant reason of the delay of system start-up time Therefore, in this paper, we present instant mounting techniques for flash file systems by storing the In-memory file system metadata to flash memory when unmounting the file system and reloading the stored metadata quickly when mounting the file system. These metadata snapshot techniques are specifically developed for NOR- and NAND-type flash memories, while at the same time, overcoming their physical constraints. The proposed techniques check the validity of the stored snapshot and use the proposed fast trash recovery techniques when the snapshot is Invalid. Based on the experimental results, the proposed techniques can reduce the flash mounting time by about two orders of magnitude over the existing de facto standard flash file system, JFFS2.

• The KIPS Transactions:PartC
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• v.14C no.1 s.111
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• pp.87-94
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• 2007

In mobile ad hoc networks the most popular on demand routing protocols are the Dynamic Source Routing (DSR) protocol and the Ad hoc On demand Distance Vector (AODV) routing protocol. These and other representative standard routing protocols are designed to find and maintain only a single path. Whenever there is a link break on the active route, source node has to invoke a route discovery process from the beginning and it causes a lot of overhead. Multipath routing protocols, which can alleviate these problems by establishing multiple alternative paths between a source and a destination, are widely studied. In this paper we propose a node disjoint multipath discovery technique based on AODV local route discovery. This technique can find and build completely separated node disjoint multi paths from a source to a destination as many as possible. It will make routing more robust and stable.

• Information and Communications Magazine
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• v.9 no.9
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• pp.72-85
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• 1992

The throughput requirement for many digital signal processing is such that multiple processing units are essential for real-time implementation. Advances in VLSI technology make it feasible to design and implement computer systems consisting of a large number of function units. The research on a very high throughput VLSI architecture for digital signal processing applications requires the development of an algorithm, decomposition scheme which can minimize data communication requirements as well as minimize computational complexity. The objectives of the research are to investigate computationally efficient algorithms for solution of the class of problems which can be modeled as DLSI systems or adaptive system, and develop VLSI architectures and associated multiprocessor systems which can be used to implement these algorithms in real-time. A new VLSI architecture for real-time 2-D digital signal processing applications is proposed in this research. This VLSI architecture extends the concept of having a single processing units in a chip. Because this VLSI architecture has the advantage that the complexity and the number of computations per input does not increase as the size of the input data in increased, it can process very large 2-D date in near real-time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.52-57
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• 2011

This paper presents a 4-channel optical transmitter circuit realized in a $0.18{\mu}m$ CMOS technology for high-speed digital interface. Particularly, the VCSEL driver exploits the feed-forward technique, and the pre-amplifier employs the pulse-width control. Thus, the optical transmitter operates at the bias current up to 4mA and the modulation current from $2{\sim}8mA_{pp}$. with the pulse-width distortion compensated effectively. The 4-channel optical transmitter array chip occupies the area of $1.0{\times}1.7mm^2$ and dissipates 35mW per channel at maximum current operations from a single 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.28-36
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• 2008

This paper discusses theimplementation of the low-voltage, low-power, third-order, 1-bit switched capacitor delta-sigma modulator of the implantable cardiac pacemaker. The distributed, feed-forward structure and bulk-driven OTA were used in order to achieve an efficient operation under a supply voltage of 1V or lower. The designed modulator has a dynamic range of 49dB at 0.9V supply voltage and consumes 816nW of power. Such a significant reduction in power consumption allows diverse applications, not only in pacemakers, but also in implantable biomedical devices that operate with limited battery power. The core chip size of the modulator is $1000{\mu}m*500{\mu}m$ manufactured, with the $0.18{\mu}m$ CMOS standard process.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.22-29
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• 1998

In this paper, an 10 bit current-mode CMOS A/D converter with a current predictor is designed with a CMOS process to be integrated into a portable image signal processing system. A current predictor let the number of comparator reduce to 70 percent compared with the two step flash architecture. The current magnitude of current reference is reduced to 68 percent with a modular current reference. The designed 10 bit Low-power current-mode CMOS A/D converter with a current predictor is simulated with HSPICE using 0.6$\mu\textrm{m}$ N-well single-poly triple-metal CMOS process parameters. It results in a conversion rate of 10MSamples/s. A power consumption is measured to be 94.4mW at single +5V supply voltage. The 10 bit A/D converter fabricated using the same process occupies the chip area of 1.8mm x 2.4mm.