• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.149-159
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• 2003

The need for information security increases interests on cipher algorithms recently. Especially, a large volume of data transmission over high-band communication network requires faster encryption and decryption techniques for real-time processing. It would be a good solution for this problem that we implement the cipher algorithm in forms of hardware circuits. Though some previous researches use this approach, they focus only on repeatedly executing the core part of the algorithm to minimize the hardware chip size, while most cipher algorithms are inherently parallel. In this paper, we propose a new design for the SEED block cipher algorithm developed by KISA (Korea Information Security Agency) in 1998 as Korean standard cipher algorithm. It exploits the parallelism of the algorithm basically and implements it in a pipelined fashion. We described the design in VHDL program and performed functional simulations on the program, and then found that it worked correctly. In addition, we synthesized it and verified that it could be implemented in a single FPGA chip, implying that the new design can be Practically used for the actual hardware implementation of a high-speed and high-performance cipher system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.77-83
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• 2009

In this paper, a selective feedback low-noise amplifier (LNA) has been realized in a $0.18{\mu}m$ CMOS technology to cover a number of wireless multi-standards. By exploiting notch filter, the SF-LNA demonstrates the measured results of the power gain (S21) of 11.5~13dB and the broadband input/output impedance matching of less than -10dB within the frequency bands of 820~960MHz and 1.5~2.5GHz, respectively. The chip dissipates 15mW from a single 1.8V supply, and occupies the area of $1.17\times1.0mm^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1195-1201
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• 2005

This paper deals with procedures and results for teal time implementation of G.729 speech coder and channel coder including convolution codec, viterbi decoder, and interleaver using a fixed point DSP chip for radio communication systems. We described the method for real-time implementation based on integer simulation results and explained the implemented results by quality performance and required complexity for real-time operation. The required complexity was 24MIPS and 9MIPS in computational load, and 12K words and 4K words in execution code length for speech and channel. The functional evaluation was performed into two steps. The one was bit exact comparison with a fixed point C code, the other was executed by actual speech samples and error test vectors. Unlik other results such as individual implementation, We implemented speech and channel coders on a DSP chip with 160MIPS computation capability and 64 K words memory on chip. This results outweigh the conventional methods in the point of system complexity and implementation cost for radio communication system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.44-53
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• 2008

In this paper, we present the design of delta-sigma modulation-based class-D amplifier for driving headphones in portable audio applications. The presented class-D amplifier generates PWM(pulse width modulation) signals using a single-bit fourth-order high-performance delta-sigma modulator. To achieve a high SNR(signal-to-noise ratio) and ensure system stability, the locations of the modulator loop filter poles and zeros are optimized and thoroughly simulated. The test chip is fabricated using a standard $0.18{\mu}m$ CMOS process. The active area of the chip is $1.6mm^2$. It operates for the signal bandwidth from 20Hz to 20kHz. The measured THD+N(total harmonic distortion plus noise) at the $32{\Omega}$ load terminal is less than 0.03% from a 3V power supply.

• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 2002.02a
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• pp.192-197
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• 2002

1. 실시간 모니터링 -온실 내부환경의 계측장치로 모듈화된 단일 칩 마이크로프로세서를 이용한 하우스 모니터를 개발하였다. 개발된 다수의 하우스 모니터는 RS-485통신을 이용하여 개발된 프로토콜을 통하여 그룹 모니터와 통신하면서 계측 데이터를 전송하였고 안정된 계측 성능을 보였다. 또한 그룹 모니터는 하우스모니터로부터 수신한 데이터를 인터넷 환경 TCP/IP 통신에 의해 서버에 정보를 전송하고 데이터베이스 서버에 저장할 수 있었다. 2. 클라이언트 서버 모델 -클라이언트 모니터를 통하여 허용된 사용자들은 해당 온실의 상황을 원격지에서 파악할 수 있는 있었다. 또한 분산환경 기술을 이용하여 서버를 경유하여 데이터베이스 서버에서 데이터 셋을 가져와 과거 재배 사례 등을 조회 및 이용 가능하였다. 이는 전문가에게 접근을 허용함으로써 재배에 관한 지원이 가능하도록 하였다. 데이터 베이스 시스템으로 연계하여 온실환경 정보를 분석하는 것이 가능하였다. 3. 기대효과 및 나아가야 할 방향 -개발된 시스템을 식물 공장 내 작물의 재배환경을 데이터베이스화하여 재배사례 데이터베이스를 형성하고 작물이 가장 잘 자라는 최적 재배 환경을 연구하여 고품질의 작물 재배에 이용될 수 있다. 또한 식물공장의 운전실적, 환경 조건, 환경 조절비용 등의 분석에 효율적으로 이용될 수 있을 것으로 예상되며 각 환경인자들과의 관계를 구명하는데 도움을 줄 것이다. 축적된 작물의 재배 사례 데이터베이스를 이용하여 작물 특성 및 재배 연구에 도움을 줄 수 있을 것이다. 제어 장치들의 운영실적을 분석함으로써 제어 시스템의 효율적이고 경제적인 제어가 가능하도록 할 수 있을 것이다. 이들이 모두 완성되면 전문가 및 전문가 시스템으로부터 지원을 받는 지능형 식물공장이 가능할 것이다. 본 연구에서 개발한 계측 모듈 및 데이터베이스 시스템은 실제 농가에 설치된 전용선을 이용하여 실증 실험을 통해 수정·보완하여야 할 것이다. 또한 시설원예분야에서 있어서 통신체계에 대한 표준화 연구가 수행되어 앞으로 개발될 다른 시스템들과의 호환성을 갖도록 해야 할 것이다. 앞으로 온실의 경영 및 관리 데이터베이스를 개발하여 첨단온실의 통합 관리 및 정보 시스템을 구축하여야 할 것이다. 또한, 시설원예의 환경 설계의 기준을 적용할 수 있도록 하여야 할 것이다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.7-16
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• 2007

In this paper, we introduce a new design environment for efficient multiprocessor system-on-chip design space exploration. The design environment takes a process network model as input system specification. The process network model has been widely used for modeling signal processing applications because of its excellent modeling power. However, it has limitation in predictability, which could cause severe problem for real time systems. This paper proposes a new approach that enables static analysis of a process network model by converting it to a hierarchical synchronous dataflow model. For efficient design space exploration in the early design step, mapping application to target architectures has been a crucial part for finding better solution. In this paper, we propose an efficient mapping algorithm. Our mapping algorithm supports both single bus architecture and multiple bus architecture. In the experiments, we show that the automatic conversion approach of the process network model for static analysis is performed successfully for several signal processing applications, and show the effectiveness of our mapping algorithm by comparing it with previous approaches.

• Journal of Korea Multimedia Society
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• v.16 no.1
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• pp.75-86
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• 2013

This paper presents a technique to implement embedded systems using interrupts of the one-chip microcontroller with many peripherals based on a multiple finite state machines model. The multiple finite state machine model utilizes the structure of FSMD used for hardware design and the features of flow control by interrupts. The main finite state machine corresponds to the main program and the sub-state machines corresponds to the interrupt subroutines. Therefore, interrupts from the peripherals can be processed immediately in the sub-state machines. The request and reply variables are used to interface between the finite state machines. Additional operating system is not necessary for the context switching between the main state machine and the sub-state machine, because the flow-control caused by interrupt can be replaced with the switching. An embedded system modeled on multiple finite state machine with ASM charts can be easily implemented by the conversion of ASM charts into C-language programs. This implementation technique can be easily adopted to the hardware oriented embedded systems because of the detail description of the model and the fast response to the interrupt events in the sub-state machine.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.3
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• pp.73-77
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• 2015

This paper presents integrated polymeric spectrometer module which offers compact size, easily-fabricated structure and low cost. The proposed spectrometer module includes the nano diffraction grating with non-uniform pitch and planar optical waveguide with concave mirror to be fabricated by UV imprint lithography. To increase the reflection efficiency, we designed the nano diffraction grating with triangular profiles. The polymeric planar spectrometer includes a spectral bandwidth of 700 nm, resolution of 10 nm and precision below 5 nm. This polymeric planar spectrometer is well-suited for sensor system.

• The Transactions of the Korea Information Processing Society
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• v.4 no.6
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• pp.1565-1575
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• 1997

A new encryption algorithm had been proposed as a replacement to the Data Encryption Standard (DES) in [1,2]. It called the Extended DES (EDES) has a key length of 112 bits. The plaintext data consists of 96 bits divided into 3 sub-blocks of 32 bits each. The EDES has a potentially higher resistance to differential cryptanalysis that the DES due to the asymmetric number of f functions performed on each of the 3 sub-blocks and due to the increase of S-boxes from 8 to 16. This paper propose a hardware design for the EDES and its implementation in VLSI. The VLSI chip implements data encryption and decryption in a single hardware unit. With a system clock frequency of 15Mhz the device permits a data conversion rate of about 90Mbit/sec. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.2
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• pp.131-137
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• 2005

Protective relays provide important features to electrical power systems for protecting against faults and consequent short circuits. This research presents a novel VLSI design of the digital protective relay, which overcomes today's uP/DSP-based relays. This design features good cancellation of DC/k-th harmonic components, noticeable not performance and flexible Protection behavior in the minimized core area The proposed design was successfully implemented by a FPGA(Field Programmable Gate Array) device and can concurrently process over 16KSPS at less $0.03[\%]$ error rate.