• Proceedings of the Korean Society of Computer Information Conference
• /
• 2020.01a
• /
• pp.203-205
• /
• 2020

본 논문에서는 게임 엔진에서 사용되는 노말맵(Normal Map)의 원리와 그 응용 방식에 대해 연구하였다. 노말맵은 게임에서 하이 폴리곤 모델링에 적용되는 조명 적용 데이터를 로우 폴리곤에 적용할 수 있는 기술로, 하이 폴리곤 모델링의 벡터 방향 데이터를 텍스쳐로 저장하여 로우 폴리곤에 적용해서 벡터 방향을 텍셀단위로 조정할 수 있게 한다. 여기에서는 게임에서의 노말맵 저장 방식과 연산 방식에 대해 소개하고 이를 응용하여 최적화 시킬 수 있는 방법에 대해 연구한다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.6A
• /
• pp.631-639
• /
• 2004

In this paper, we presented a new interference suppression method based on code grouping and groupwise decorrelation for multirate DS-CDMA downlink. The code grouping is accomplished according to the correlation property between the mother code and the child codes in OVSF code tree. Using groupwise decorrelation, the proposed receiver has relatively low computational complexity and does not require any information about interference users, such as code, data, and amplitude. From the simulation results in multipath channels, the proposed receiver is to provide significant performance enhancement.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.41 no.6
• /
• pp.253-260
• /
• 2004

This paper proposes a novel algorithm for hybrid lossless audio coding, which employs an integer wavelet transform and a linear prediction model. The proposed algorithm divides the input signal into flames of a proper length, decorrelates the framed data using the integer wavelet transform and linear prediction and finally entropy-codes the frame data. In particular, the adaptive Golomb-Rice coding method used for the entropy coding selects an optimal option which gives the best compression efficiency. Since the proposed algorithm uses integer operations, it significantly improves the computation speed in comparison with an algorithm using real or floating-point operations. When the coding algorithm is implemented in hardware, the system complexity as well as the power consumption is remarkably reduced. Finally, because each frame is independently coded and is byte-aligned with respect to the frame header, it is convenient to move, search, and edit the coded, compressed data.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.1
• /
• pp.205-212
• /
• 2010

This paper describes a core generator (FCore_Gen) which generates Verilog-HDL models of 640 different FFT/IFFT cores with selected parameter value for OFDM-based communication systems. The generated FFT/IFFT cores are based on in-place single memory architecture and use a hybrid structure of radix-4 and radix-2 DIF algorithm to accommodate various FFT lengths. To achieve both memory reduction and the improved SQNR, a conditional scaling technique is adopted, which conditionally scales the intermediate results of each computational stage. The cores synthesized with a $0.35-{\mu}m$ CMOS standard cell library can operate with 75-MHz@3.3-V, and a 8,192-point FFT can be computed m $762.7-{\mu}s$, thus the cores satisfy the specifications of wireless LAN, DMB, and DVB systems.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.2
• /
• pp.329-334
• /
• 2014

This paper proposes the hardware architecture of high performance multi-mode 2D forward transform for HEVC which has same number of cycles for processing any type of four TUs and yield high throughput. In order to make the original image which has high pixel and high resolution into highly compressed image effectively, the transform technique of HEVC supports 4 kinds of pixel units, TUs and it finds the optimal mode after performs each transform computation. As the proposed transform engine uses the common computation operator which is produced by analyzing the relationship among transform matrix coefficients, it can process every 4 kinds of TU mode matrix operation with 35cycles equally. The proposed transform block was designed by Verilog HDL and synthesized by using TSMC 0.18um CMOS processing technology. From the results of logic synthesis, the maximum operating frequency was 400MHz and total gate count was 214k gates which has the throughput of 10-Gpels/cycle with the $4k(3840{\times}2160)@30fps$ image.

• Proceedings of the Korea Water Resources Association Conference
• /
• 2018.05a
• /
• pp.453-453
• /
• 2018

2017년 12월 기준 우리나라에 등록된 자동차는 약 2,200만 이상으로, 그 증가율은 매년 증가하는 추세이다. 이러한 최근 차량대수 및 고자산인 외산차 보유율 증가는 자연재난에서 노출과 관련한 위험도를 증가시키는 주요인이 되며, 홍수발생 시 상당한 규모의 경제적 피해를 야기한다. 현재 국가연구개발사업으로 진행 중인 행정안전부(2017) 연구는 위험지역 내 차량의 공간적 분포와 차량유형별 침수심에 따른 취약성을 고려하여 어떠한 홍수사상으로부터 예상되는 차량 피해액을 추정하는 방법을 제시한 바 있다. 여기서는 어떠한 집계구 내에서 동일한 침수심 구간을 가지는 면(polygon)을 분석단위로 하고 있는 데, 이를 편의성 차원에서 벡터자료에 기반 한 연산과정을 수행할 경우 정의된 침수구역도(재해정보)의 고유 정보가 훼손되거나, 세분화된 침수심 구간에 따른 손상률 관계를 사용할 수 없는 문제점이 있다. 이에 본 연구에서는 격자 기반의 침수구역도와 인벤토리 지도로부터 Raster GIS 공간연산을 활용한 차량피해 산정절차를 제시하였고, 이를 신천수계 하천기본계획(경기도, 2011)에서 계획된 치수사업에 적용하여 홍수빈도별 사업시행 전후 상황에 적용하였다. 이 과정에서 침수구역도는 인벤토리 상의 집계구 면적을 고려하여 $5m{\times}5m$ 크기로 제작하였고, 동일한 격자크기로 변환된 인벤토리는 변환 전후 면적을 기준으로 할 때 거의 오차가 없는 것으로 확인되었다. 그리고 Raster 공간연산으로부터 침수편입률을 결정하는 과정에서 집계구 넘버 및 침수심 정보를 확인하기 위한 자료별 전처리 과정을 제시하였고, 여기서 집계구 넘버는 인벤토리 정보와 침수심 정보는 손상함수와 연계된다. 본 연구에서 제시한 결과는 향후 실무에서 직접 적용하는 데 활용하기 위하여 방법론과 함께 가이드라인 문서로 정리할 계획이다.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.11 no.1
• /
• pp.64-72
• /
• 2001

This paper is on a design of the high-speed cipher IC using IDEA algorithm. The chip is consists of six functional blocks. The principal blocks are encryption and decryption key generator, input data circuit, encryption processor, output data circuit, operation mode controller. In subkey generator, the design goal is rather decrease of its area than increase of its computation speed. On the other hand, the design of encryption processor is focused on rather increase of its computation speed than decrease of its area. Therefore, the pipeline architecture for repeated processing and the modular multiplier for improving computation speed are adopted. Specially, there are used the carry select adder and modified Booth algorithm to increase its computation speed at modular multiplier. To input the data by 8-bit, 16-bit, 32-bit according to the operation mode, it is designed so that buffer shifts by 8-bit, 16-bit, 32-bit. As a result of simulation by 0.25 $\mu\textrm{m}$ process, this IC has achieved the throughput of 1Gbps in addition to its small area, and used 12,000gates in implementing the algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.12
• /
• pp.1904-1913
• /
• 2021

With the proliferation of smart phones and the development of IoT technology, it has become possible to collect personal data for public purposes. However, users are afraid of voluntarily providing their private data due to privacy issues. To remedy this problem, mainly three techniques have been studied: data disturbance, traditional encryption, and homomorphic encryption. In this work, we perform simulations to compare them in terms of accuracy, message length, and computation delay. Experiment results show that the data disturbance method is fast and inaccurate while the traditional encryption method is accurate and slow. Similar to traditional encryption algorithms, the homomorphic encryption algorithm is relatively effective in privacy preserving because it allows computing encrypted data without decryption, but it requires high computation costs as well. However, its main cost, arithmetic operations, can be processed in parallel. Also, data analysis using the homomorphic encryption needs to do decryption only once at any number of data.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.12 no.4
• /
• pp.291-299
• /
• 2007

To operate a permanent magnet synchronous motor (PMSM) at a maximum torque per ampere (MTPA) operation point, the exact values of machine parameters such as inductances and back-EMF constant, which are sensitive to motor phase currents and temperature respectively, should be blown. An adaptive estimation method for on-line estimation of the machine parameters is not suitable for practical applications since it has difficulties in estimating exact values and requires complex mathematical calculations. The purpose of this paper is to present a simple MTPA operation point tracking control strategy for vector controlled PMSM drives with slow dynamic loads. The proposed method searches MTPA operation points by modulating current phase angle and observing the variation in command power. The current angle modulation strategy is designed to sense the effect of load variations in the command power. Therefore, the proposed method can track the MTPA operation points of the PMSM regardless of load variations. Computer simulation and experimental study is also presented to show the effectiveness of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.42 no.4 s.304
• /
• pp.167-176
• /
• 2005

This paper proposes a new power minimization technique for the frame-based multimedia signal processing. The derivation of the technique is based on the newly proposed microscopic DVS(Dynamic Voltage Scaling) method, where, the operating frequency and the supply voltage levels are dynamically controlled according to the processing requirement for each frame of multimedia data. The multimedia signal processing algorithms are also redesigned and optimized to maximize the power saving efficiency of the microscopic DVS technology. The characterization of the mean/variance distribution of the processing load in the frame-based multimedia signal processing provides the major basis not only for the optimized application of the microscopic DVS technology but also for the optimization of the multimedia algorithms. The power saying efficiency of the proposed DVS approach is experimentally tested with the algorithms of MPEG-2 video decoder and MPEG-2 AAC audio encoder on the ARM9 RISC processor. The experimental results with the diverse MPEG-2 video and audio files show The average power saving efficiencies of 50$\%$ and 30$\%$, respectively. The results also agree very well with those of the analytic derivations.