• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.2
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• pp.66-74
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• 1985

An idea is presented in this paper that control panel be implemented with a ${\mu}$-processor instead of interrupt based logic circuits. To prove that the idea is reasonable, a ${\mu}$-computer controlled traffic light control system is chosen as a model, and its control panel is imple-mented witll a f-processor. The result is that the microprocessor-based control panel performs its function very well.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.10
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• pp.78-88
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• 1990

To evaluate the performance of a multiprocessor system, a discrete event model of memory interference in the system employing multiple-bus interconnection networks is proposed. An analytic model of the system is presented and then simulator models are implemented for cross-verifying the analytic results and simulation results. The simulator model takes as input the number of processors, the number of memory modules, the number of buses and the local memory miss ratio. The model produces as output the memory bandwidth, the processor, memory module and bus utilization and the bus contention ratio. Using the model in the design of the system, it is possible to evaluate the system performance by analyzing the interaction of the input parameters.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.1
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• pp.35-44
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• 2005

This paper proposes an efficient heuristic load balancing algorithm for multiprocessor systems. The algorithm minimizes the number of idle links to distribute load traffic and reduces its communication cost. Each processor iteratively tries to transfer unit load to/from all neighbor processors. However, real load transfer is collectively done after all load traffic is calculated. This prevents useless traffic and thus reduces the overall load traffic. The proposed algorithm can be employed in various interconnection topologies with slight modifications. In this paper, it is applied to hypercube, mesh, k-ary n-cube and general graph environments. For performance evaluation, simulation studies are performed. The proposed algorithm and the well-known existing algorithms are implemented and compared. The results show that the proposed algorithm always balances the loads perfectly. furthermore, in comparison with the existing algorithms, it reduces the communication costs by 77%, 74% and 73% in the hypercube, the mesh, and k-ary n-cube, respectively.

• The KIPS Transactions:PartA
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• v.13A no.2 s.99
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• pp.157-162
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• 2006

Recent High Performance Computing (HPC) platforms can be classified as Shared-Memory Multiprocessors (SMP), Massively Parallel Processors (MPP), and Clusters of computing nodes. These platforms are deployed in many scientific and engineering applications which require very high demand on computing power. In order to realize an optimal performance for these applications, it is crucial to find and use the suitable computing platforms and programming paradigms. In this paper, we use SPEC HPC 2002 benchmark suite developed in various parallel programming models (MPI, OpenMP, and hybrid of MPI/OpenMP) to find an optimal computing environments and programming paradigms for them through their performance analyses.

• Journal of Korean Electronics
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• v.8 no.3
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• pp.66-74
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• 1988

• The Magazine of the IEIE
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• v.21 no.4
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• pp.1-7
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• 1994

• The Journal of Korean Association of Computer Education
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• v.17 no.1
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• pp.107-115
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• 2014

This paper evaluates and analyzes the performance of TILE-Gx36(Gx36), a many-core processor. The PARSEC parallel benchmark suite was used to measure the performance, and Core i7 (i7) and Atom are used for the performance comparison. When experimented with the maximum number of threads that can be executed concurrently on each machine, Gx36 showed a 2.73${\times}$ inferior performance to Core i7 and a 1.93${\times}$ superior performance to Atom. Gx36 has the largest Last Level Cache(LLC) among the compared processors. Nevertheless, it reported the biggest number of LLC misses, which, we strongly believe, is the major culprit for lower performance than expected. Our study suggests that the DDC employed in Gx36 is not a favorable cache structure for the general-purpose high-performance computing. The actual measurement with off-the-shelf machine provides non-biased data for polishing the future many-core architecture.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.9
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• pp.487-494
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• 2004

The multiprocessor system suffers interconnection network contension while exploiting the program's parallelism. A CC-NUMA system based on point-to-point link ring structure is one of the scalable architectures that expand the system bandwidth the number of processors/nodes increases. The dual-ring system is a simple solution to enhance the system performance and scalability by duplicating the links. In ring-based systems, an unbalanced transaction among links makes a hot spot on the interconnection network. In this situation, total system performance and scalability are bound by the hot spot of the links In this paper, I propose a dual-link CC-NUMA system, which alleviates the concentration of transactions among the links. By the simulation results, the proposed system significantly outperforms the single-ring and bidirection dual-ring systems. In addition, the proposed system show better distribution of transactions among the links that achieves an extended scalability.

• The Transactions of the Korea Information Processing Society
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• v.5 no.5
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• pp.1151-1161
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• 1998

In this paper, we are considering a heterogeneous processor system in which each processor may have different performance and reliability characteristics. In other to fully utilize this diversity of processing power it is advantageous to assign the program modules of a distributed program to the processors in such a way that the execution time of the entire program is minimized. This assignment of tasks to processors to maximize performance is commonly called load balancing, since the overloaded processors can perform their own processing with the performance degradation. For the task assignment problem, we propose a new objective function which formulates this imbalancing cost. Thus the task assignment problem is to be carried out so that each module is assigned to a processor whose capabilities are most appropriate for the module, and the total cost is minimized that sum of inter-processor communication cost and execution cost and imbalance cost of the assignment. To find optimal assignment is known to be NP-hard, and thus we proposed an efficient heuristic algorithm with time complexity $O(n^2m)$ in case of m task modules and n processors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.366-373
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• 2007

In this paper we propose a multi-channel speech pickup system for calling quality enhancement of hands-free communication using ALTERA Nios-II processor. Multi-channel speech pickup system uses Delay-and-Sum beamformer with zero-padding interpolator. This paper implements speech pickup system using the Nios-II processor with real-time I/O data processing speed. The proposes speech pickup embedded system shows a good agreement with those of computer simulation(MATLAB) and conventional DSP processor(TMS320C6711) result. The proposed method is effective more than previous methods in cost and design processing time. As a result, LE(Logic Element) of hardware used 3,649/5,980(61%) on a chip.