• Journal of KIISE:Computing Practices and Letters
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• v.6 no.4
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• pp.383-392
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• 2000

Currently, multiprocessors are evaluated almost exclusively with scientific applications. Commercial applications are rarely explored because it is difficult to obtain the source codes of commercial DBMS. Even when the source code is available, such as for POSTGRES, understanding the source code enough to perform detailed meaningful performance evaluations is a daunting task for computer architects.To evaluate multiprocessors with commercial applications, we have developed our own DBMS, called EZDB. EZDB is a parallelized DBMS, loosely inspired from POSTGRES, and running on top of a software architecture simulator. It is capable of executing parallel programs written in SQL. Contrary to POSTGRES, EZDB is not intended as a prototype for a production-quality DBMS. Its purpose is to easily run and evaluate the performance of commercial applications on multiprocessor architectures. To illustrate the usefulness of EZDB, we showed the cache performance data collected for the TPC-B benchmark on a shared-memory multiprocessor. The simulation results showed that the data structures exhibited unique sharing characteristics and that their locality properties and working sets were very different from those in scientific applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2801-2809
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• 1996

Scheduling problems in real-time systems are known to be NP-hard. the heuristic approaches aregenerally aplied to solve a certain class of systems. One of such cases is to allocate periodic tasks to multiprocessors while the moethod assures the requirement of the deadine constraints of real-time systems. The study on the allocation of periodic taks includes RMNF, RMFF, FFDUF and Next-Fit-M algorithms, which make a set of task grups first and then allocate to processors. This papre proposes the various algorithms which are based on the Next-Fit-M. To analyze the four proposed methods, simulation was carried on, in which the sample tasks are randomly generated with the various time intervals. The proposed algorithms reduce the number of processors compared with the conventional methods.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.6
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• pp.558-566
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• 2000

Object recognition is a challenging application for high-performance computing. Currently, the superscalar architecture dominates todays microprocessor marketplace. As more transistors are integrated onto larger die, however, an on-chip multiprocessor is regarded as a promising alternative to the superscalar microprocessor. This paper examines the behavior of the object recognition on the on-chip multiprocessor, which will be employed in general-purpose parallel machines. To obtain the performance characteristics of the microprocessor, a program-driven simulator and its programming environment were developed. The simulation results showed that the on-chip multiprocessor can exploit thread level parallelisms effectively and offer a promising architecture for the object recognition application.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.3
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• pp.337-344
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• 2000

In this paper, we define a Process Algebra ACSMR(Algebra of Communicating Shared Multiple Resources) for system specification and verification using multiple resources. ACSMR extends a concept of multiple resources in ACSR that is a branch of formal methods based on process algebra. We'll show that two specification and verification examples. One is the specification of system behavior in multiprocessor using EDF(Earliest-Deadline-First) which is a scheduling algorithm of a real-time system. The other is the specification of describing timing analysis and resources restriction in a super scalar processor using multiple ports registers.

• Proceedings of the Korea Society for Simulation Conference
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• 1998.10a
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• pp.161-165
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• 1998

다중 프로세서 구조로 실시간 분산 처리를 하는 전전자 교환기 시스템은 그 특성상 2개 이상의 프로세서에 동일한 값을 유지하는 중복 데이터의 사용이 필수적이다. 시스템의 자원 정보, 번호 번역 정보, 과금 정보 등이 중복 데이터로 사용된다. 이러한 중복 데이터에 대한 변경은 불일치 상태를 회피하기 위해 그 처리에 많은 비용과 제한이 따른다. 과도한 시그널 전송 및 로그 저장, 재전송 알고리즘은 데이터베이스 시스템의 성능을 저하시키고 때때로 순간적인 마비 상태까지도 유발할 수 있다. 본 논문에서는 기존 일관성 방안의 문제점을 분석하고 단일-버스 다중-프로세서 시스템에서 각각의 캐쉬들간의 일관성 유지를 위한 write-through 캐쉬 일관성 프로토콜을 사용하여 저 비용이며 효율적인 중복 데이터 일관성 유지 방안을 제시한다.

• The Transactions of the Korea Information Processing Society
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• v.5 no.8
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• pp.2164-2178
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• 1998

본 논문에서는 한 사이클에 여러 개의 명령들이 다중 이슈되어 명령어 수준에서 병렬처리되는 ILP 프로세서의 성능을 측정하고 평가하는 시스템을 개발한다. 개발되는 시스템은 C 컴파일러와 시뮬레이터로 구성된다. C 컴파일러는 C 소스 프로그램을 입력으로 받아 3-주소 코드형태의 중간언어를 생성한다. 생성된 중간언어는 ILP 프로세서의 환경 파라미터와 함께 시뮬레이터에 입력되어 시뮬레이션된 후 메모리 내용, 수행된 클럭 수 및 명령 트레이스, 수행된 명령들의 동적 빈도수, 분기명령의 예측률, profiling 정보 등을 생성한다. 개발된 성능측정 시스템의 동작 검증을 위하여 순차이슈 되어 정적으로 스케쥴링 되는 조건실행 방식의 성능과 분기처리 방식의 성능을 측정하여 분석한다.

• The KIPS Transactions:PartA
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• v.12A no.2 s.92
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• pp.145-150
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• 2005

Recently, many Processor manufacturers have implemented simultaneous multi treading technology, which can simultaneously execute independent threads in one processor cycle, as a way of increasing processor efficiency, ana one particular example is Hyper Threading. Hyper Threading technology, which enables many logical processors to reside a physical processor, differs from the current multiprocessing environment which has many independent processors, and calls for a particular work assignment method optimized for Hyper Threading environment Thus, in this paper, We have proposed a scheduling algorithm compatible with Hyper Threading technology and analyzed its performance using various methods. As a result, we shall expect its efficient performance by properly understanding and managing Hyper Threading system.

• Journal of the Korea Society of Computer and Information
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• v.12 no.3
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• pp.147-153
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• 2007

Task scheduling is an essential part of any computer system for allocating tasks to a processor of the system among various competitors. As we know, in real-time system, the failure of scheduling a hard real-time task my lead to disastrous consequence. Besides efficiency, resource and speed, real-time system has to take time constraint in serious consideration. This paper proposes a priority-driven scheduling algorithm for real-time multiprocessor system. which is called L-RE coordinates algorithm. L-RE coordinates is a new way of describing the task scheduling problem. In the algorithm, we take both deadline and laxity into consideration for allocating the priority. The simulation result shows that the new algorithm is viable and performance better than EDF and LLF algorithm on schedulability and context switch respectively.

• Journal of the Korean Institute of Intelligent Systems
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• v.18 no.3
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• pp.323-328
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• 2008

This paper presents a Digital Signal Processor achieving high through-put for both decision intensive and computation intensive tasks. The proposed processor employees a multiplier, two ALU and load/store. Unit as operational units. Those four units are controlled and works parallel by superscalar control scheme, which is different from prior DSP architecture. The performance evaluation was done by implementing AC-3 decoding algorithm and 37.8% improvement was achieved. This study is valuable especially for the consumer electronics applications, which require very low cost.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.5
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• pp.297-305
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• 2006

Trace-driven simulation is widely used for measuring the performance of a microprocessor in its initial design phase. However, since it requires much time and disk space, the statistical simulation has been studied as an alternative method. In this paper, statistical simulations are performed for a high performance superscalar microprocessor with a perceptron-based multiple branch predictor. For the verification, various hardware configurations are simulated using SPEC2000 benchmarks programs as input. As a result, we show that the statistical simulation is quite accurate and time saving for the evaluation of microprocessor architectures with multiple branch prediction.