• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.10
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• pp.1858-1865
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• 2007

In this paper, we introduce the design and implementation of satellite IP modem. The designed satellite IP modem shows the performance of 0.2% overhead, BER=10-5 when Eb/No=6dB, frequency offset of 8KHz, data rate up to 1536Kbps, $F_{if}=140MHz$. The designed system is verified through software simulation and then implemented with MPC86x communication processor, TMS320C6416 DSP, and Altera FPGA. Since each hardware unit is implemented in daughter board for modularity, we can reduce the development time and easily improve the performance with using better processor. Linux is used for embedded OS because it shows better performance in IP manipulation multitask processing, and hardware control through device driver. The implemented system is tested and verified with channel simulator. Since the proposed IP modem shows small size and light weight, that can be used anywhere with easy if you need IP environment.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.1
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• pp.10-18
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• 2007

Mobile communication devices such as PDAs, cellular phones, etc., need to perform several kinds of computation-intensive functions including H.264 encoding/decoding and 3D graphics processing. In this paper, new reconfigurable architecture is described, which can perform either motion estimation for H.264 or rendering for 3D graphics. The proposed motion estimation techniques use new efficient SAD computation ordering, DAU, and FDVS algorithms. The new approach can reduce the computation by 70% on the average than that of JM 8.2, without affecting the quality. In 3D rendering, midline traversal algorithm is used for parallel processing to increase throughput. Memories are partitioned into 8 blocks so that 2.4Mbits (47%) of memory is shared and selective power shutdown is possible during motion estimation and 3D graphics rendering. Processing elements are also shared to further reduce the chip area by 7%.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.68-75
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• 2016

As the number of cores and IPs increase in multiprocessor system-on-chip (MPSoC), network-on-chip (NoC) has emerged as a promising novel interconnection architecture for its parallelism and scalability. However, minimization of the latency in NoC with legacy bus IPs must be addressed. In this paper, we focus on the latency minimization problem in NoC which accommodates legacy bus protocol based IPs considering the trade-offs between hop counts and path collisions. To resolve this problem, we propose separated address/data network for independent address and data phases of bus protocol. Compared to Mesh and irregular topologies generated by TopGen, experimental results show that average latency and execution time are reduced by 19.46% and 10.55%, respectively.

• The Magazine of the IEIE
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• v.19 no.4
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• pp.1-7
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• 1992

IBM이 16비트 PC를 처음 선보인 81년 이후 오늘에 이르기까지 10여년간의 운영체제(0S) 시장은 마이크로소프트(MS)사의 독주시대로 요약할 수 있다. 그러나 지금까지 이렇다 할 변화를 보이지 않던 OS제품은 90년대에 들어서면서 커다란 변화의 조짐에 횝싸이고 있다. 그동안 8086, 80286등의 마이크로프로세서를 탑재한 16비트 PC시장이 80386,80486등을 탑재한 32비트 시장으로 급변하기 시작했고 종전 데스크탑 일변도의 PC시장은 랩톱,노트북형 등의 휴대형컴퓨터와 펜컴퓨터,멀티미디어 등의 차세대 제품등으로 세분화되기 시작한 것이다. 또 32비트 시대가 다가오면서 한사람이 한 대의 PC로 일을 하는 종전 PC운용환경은 넷워킹과 멀티테스킹이 강조되는 다중작업 환경으로 전환되고 있으며 윈도즈(Windows) 3.0의 대히트로 IBM PC에서도 GUI(그래픽 사용자인터페이스) 환경을 요구, 이를 위한 새로운 05의 등장이 불가피해지고 있다. 게다가 지금까지 메인프레임을 중심으로 한 중앙집중방식의 컴퓨터환경이 다운사이징화 되면서 넷워크 환경을 기반으로 한 PC의 역할이 크게 강조, 이를 위한 운영체제 또한 새로운 영역으로 대두되고 있다. 불과 1∼2년 사이에 급진전되고 있는 이같은 변화의 물결은 필연적으로 다양한 운영체제의 개발을 가져왔고 이를 통해 차세대 PC시장을 주도하기 위한 업계의 패권다툼은 전쟁을 방불케할 만큼 치열해지고 있다. MS사의 전유물이었던 DOS 영역에서는 최근 노벨사와의 합병으로 전열을 가 다듬은 디지틀리서치사가 가세, 한판승부를 선언하고 나섰으며 고성능 PC시대의 패권을 잡기 위해 10년지기였던 IBM과 MS사는 각각 OS/2와 윈도즈를 내세우고 양보할 수 없는 힘겨루기에 들어갔다. 또 이들 양사는 펜컴퓨터,멀티미디어등 차세대제품의 운영체제 시장을 둘러싸고 일찍부터 격전에 들어갔으며 IBM과 MS사의 혼전을 틈타 썬마이크로시스템을 필두로한 워크스테이션 업체 및 유닉스진영까지 고성능 PC시장을 겨냥한 OS를 속속 개발, 90년대의 OS 전쟁은 한치 앞을 내다볼 수 없는 안개국면으로 접어들고 있다. DOS에서 32비트시대,펜컴퓨터, 멀티미디어에 이르는 차세대제품을 둘러싼 업계의 OS 쟁탈전을 통해 OS의 발전동향과 미래를 전망해 본다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.38-44
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• 2008

In this paper, we introduce an low complexity and low power IR-UWB (impulse radio ultra wideband) baseband transceiver for wireless sensor network. The proposed baseband, implemented by TSMC 0.18um CMOS technology, has a simple structure in which a simplified packet structure and a digital synchronizer with 1-bit sampler to detect incoming pulses are used. Besides, clock gating method using gated clock cell as well as customized clock domain division can reduce the total power consumption drastically. As a result, the proposed baseband has about 23K digital gates with an internal memory of 2Kbytes and achieves about 1.8mW@1Mbps power consumption.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.3
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• pp.8-14
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• 2012

Improving the speed of image processing is in great demand according to spread of high quality visual media or massive image applications such as 3D TV or movies, AR(Augmented reality). SIMD computer attached to a host computer can accelerate various image processing and massive data operations. MAMS is a multi-access memory system which is, along with multiple processing elements(PEs), adequate for establishing a high performance pipelined SIMD machine. MAMS supports simultaneous access to pq data elements within a horizontal, a vertical, or a block subarray with a constant interval in an arbitrary position in an $M{\times}N$ array of data elements, where the number of memory modules(MMs), m, is a prime number greater than pq. MAMS-PP4 is the first realization of the MAMS architecture, which consists of four PEs in a single chip and five MMs. This paper presents implementation of image processing algorithms and performance analysis for MAMS-PP16 which consists of 16 PEs with 17 MMs in an extension or the prior work, MAMS-PP4. The newly designed MAMS-PP16 has a 64 bit instruction format and application specific instruction set. The author develops a simulator of the MAMS-PP16 system, which implemented algorithms can be executed on. Performance analysis has done with this simulator executing implemented algorithms of processing images. The result of performance analysis verifies consistent response of MAMS-PP16 through the pyramid operation in image processing algorithms comparing with a Pentium-based serial processor. Executing the pyramid operation in MAMS-PP16 results in consistent response of processing time while randomly response time in a serial processor.

• The KIPS Transactions:PartD
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• v.9D no.5
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• pp.755-768
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• 2002

We investigate the effect of the data skew of join attributes on the performance of a pipelined multi-way hash join method, and propose two new hash join methods with load balancing capabilities. The first proposed method allocates buckets statically by round-robin fashion, and the second one allocates buckets adaptively via a frequency distribution. Using hash-based joins, multiple joins can be pipelined so that the early results from a join, before the whole join is completed, are sent to the next join processing without staying on disks. Unless the pipelining execution of multiple hash joins includes some load balancing mechanisms, the skew effect can severely deteriorate system performance. In this paper, we derive an execution model of the pipeline segment and a cost model, and develop a simulator for the study. As shown by our simulation with a wide range of parameters, join selectivities and sizes of relations deteriorate the system performance as the degree of data skew is larger. But the proposed method using a large number of buckets and a tuning technique can offer substantial robustness against a wide range of skew conditions.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.2
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• pp.110-116
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• 2013

The amplification rate of a RF repeater is limited by the feedbacked signals from the same repeater. And an ICS (Interference Cancellation System) repeater has been developed to remove the feedbacked signals. The ICS repeater estimates the amplitudes and the phases of the feedbacked signals and removes the estimated feedback signals from the received input signal of the repeater. However, it requires lots of hardware complexity and this leads to the increase the cost of the repeater. Moreover, the ICS repeater can not solve the pilot pollution problems. To solve these problems, we have studied the implementation and adaptation of smart antenna system for RF repeaters. We have designed a smart antenna system with a switching beam structure in order to reduce the hardware and computational complexity. After analyzing the proposed smart antenna system, we found out that the amplification rate of the proposed repeater increases 23dB compare to the amplification rate of ICS repeater and the output SINR increases 6dB compare to the ICS repeater.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.25-32
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• 2011

Networks-on-chip (NoC) is emerging as a key technology to overcome severe bus traffics in ever-increasing complexity of the Multiprocessor systems-on-chip (MPSoC); however traditional electrical interconnection based NoC architecture would be faced with technical limits of bandwidth and power consumptions in the near future. In order to cope with these problems, a hybrid optical NoC architecture which use both electrical interconnects and optical interconnects together, has been widely investigated. In the hybrid optical NoCs, wormhole switching and simple deterministic X-Y routing are used for the electrical interconnections which is responsible for the setup of routing path and optical router to transmit optical data through optical interconnects. Optical NoC uses circuit switching method to send payload data by preset paths and routers. However, conventional hybrid optical NoC has a drawback that concurrent transmissions are not allowed. Therefore, performance improvement is limited. In this paper, we propose a new routing algorithm that uses circuit switching and adaptive algorithm for the electrical interconnections to transmit data using multiple paths simultaneously. We also propose an efficient method to prevent livelock problems. Experimental results show up to 60% throughput improvement compared to a hybrid optical NoC and 65% power reduction compared to an electrical NoC.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.37 no.9
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• pp.1093-1098
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• 2013

A single-crystal sapphire is used as a transparent bulletproof window material; however, few studies have investigated the dynamic behavior and fracture properties under high-speed impact. High-speed and high-resolution sequential images are required to study the interaction of the bullet with the brittle ceramic materials. In this study, a device is developed to capture the sequence of high-speed impact/penetration phenomena. This system consists of a speed measurement device, a microprocessor-based camera controller, and multiple CCD cameras. By using a linear array sensor, the speed-measuring device can measure a small (diameter: up to 1 2 mm) and fast (speed: up to Mach 3) bullet. Once a bullet is launched, it passes through the speed measurement device where its time and speed is recorded, and then, the camera controller computes the exact time of arrival to the target during flight. Then, it sends the trigger signal to the cameras and flashes with a specific delay to capture the impact images sequentially. It is almost impossible to capture high-speed images without the estimation of the time of arrival. We were able to capture high-speed images using the new system with precise accuracy.