• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.141-149
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• 2013

This paper presents a high-speed intrusion detection process for multi-core video surveillance systems. The high-speed intrusion detection was designed to a parallel process. Based on the analysis of the conventional process, a parallel intrusion detection process was proposed so as to be accelerated by utilizing multiple processing cores in contemporary computing systems. The proposed process performs the intrusion detection in a per-frame parallel manner, considering the data dependency between frames. The proposed process was validated by implementing a multi-threaded intrusion detection program. For the system having eight processing cores, the detection speed of the proposed program is higher than that of the conventional one by up to 353.76% in terms of the frame rate.

• The Transactions of the Korea Information Processing Society
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• v.6 no.4
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• pp.1058-1070
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• 1999

In this paper, we propose a control model which can control the burst input messages of the BSC(Base Station controller) in mobile communication systems more efficiently and reliably, by dividing the input messages characteristically and using multiprocessor system. Using M/M/c/K queueing model, we briefly analyze proposed model to get characteristic parameters which are required to performance improvement. On the base of the results, we compare our proposed model with the conventional one by using SLAM II with regard to the following factors : the call blocking rate of the input message, the distribution of average queue length, the utilization of process controller(server), and the distribution of average waiting time in queue. In addition, we modified our model which has overload control function for burst input messages, and analyzed its performance.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.10
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• pp.1-12
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• 1993

A multiprocessor system for high-speed processing of hybrid image coding algorithms such as H.261, MPEG, or Digital HDTV is presented in this study. Using a combination of highly parallel 32-bit microprocessor, DCT(Discrete Cosine Transform), and motion detection processor, a new processing module is designed for the implementation of high performance coding system. The sysyem is implemented to allow parallel processing since a single module alone cannot perform hybrid coding algorithms at high speed, and crossbar switch is used to realize various parallel processing architectures by altering interconnections between processing modules within the system.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.10
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• pp.13-26
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• 1993

Motion picture algorithms are realized on the multiprocessor system presented in the Study I. For the most efficient processing of the algorithms, pipelining and geometrical parallel processing methods are employed, and processing time, communication load and efficiency of each algorithm are compared. The performance of the implemented system is compared and analysed with reference to MPEG coding algorithm. Theoretical calculations and experimental results both shows that geometrical partitioning is a more suitable parallel processing algorithm for moving picture coding having the advantage of easy algorithm modification and expansion, and the overall efficiency is higher than pipelining.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.589-591
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• 2002

본 논문에서는 메쉬 구조의 다중처리시스템을 위한 새로운 할당방법을 제안한다. 이 할당방법은 다른 가용 서브메쉬와 중첩되지 않는 독립 가용 서브메쉬를 유형에 따라 분류하여 유형별 가용 서브메쉬 리스트를 생성한다. 그리고 태스크의 유형에 따라 해당 유형별 가용 서브메쉬 리스트에서 최적할당이 가능한 서브메쉬를 찾음으로써 서브메쉬를 탐색하는데 소요되는 시간을 줄인다. 이 때 서브메쉬를 찾지 못하면 확장지수를 이용하여 더 큰 가용 서브메쉬를 형성한 후 할당함으로써 태스크의 대기 시간을 줄이고, 이 결과로 외적단편화를 줄이는 효과도 얻는다. 또한 할당 해제시 독립 가용 서브메쉬는 다른 가용 서브메쉬의 크기 에 변화를 주지 않기 때문에 그 유형에 따라 유형별 가용 서브메쉬 리스트에 삽입한다. 그럼으로써 할당 해제 후 유형별 가용 서브메쉬 리스트를 재생성하기 위해 전체 메쉬 구조를 탐색 할 필요가 없어진다.

• The Journal of the Korea Contents Association
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• v.2 no.2
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• pp.103-111
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• 2002

In parallel application programs with a localized communication, even if the MINs have lour diameters, overall system performance degrades when compared to the hypercube and tree structure. The reason is that it is impossible for MINs to provide some mechanisms for clustering to exploit the locality of reference. However proposed MIN can be constructed suitable for localized communication by providing the shortcut path and multiple paths inside the processor-memory duster which has frequent data communications. Therefore proposed MIN achieves enhanced performance in parallel application program with a localized communication.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.906-915
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• 1988

The reliability enhancement is the critical issue in many computer applications, particulary in process control system. In this paper we describe how to achieve the reliability improvement in control system which is based on multiprocessors. The proposed method is accomplished by using the techniques of fault detection which composed by internal and external fault detections, fault isolation for removing the fault propagation, safety action for driving safe input, and fault diagnosis. This approach is experimented and asopted in boiler backup control system constructed by VMEbus system, CPU boards, graphic system, and other interface boards with UNIX operating system.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.2
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• pp.19-32
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• 1993

This paper suggests the new high-speed input/output techniques in a shared memory multiprocessor system. The high-speed I/O processor which can connect the different kinds of large sized I/O periperal devices, the communication protocol to the main processing units for I/O operations, and the job scheduling scheme are addressed. This paper also introduces the disk cache technique which supports the slow I/O devices comparing with the main processing units. These techniques were implemented in the TICOM system. The performance evaluation statistics were collected and analyzed for the suggested high-speed I/O processing techniques. These statistics show the superiority of the suggested techniques.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.5
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• pp.343-356
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• 1991

An efficient real-time implementation of digital filtering algorithms using a multiprocessor system in a ring network is investigated. The development time and cost for implementing a high speed signal processing system can be considerably reduced because algorithm are implemented in software using commercially available digital signal processors. This method is based on a parallel block processing approach, where a continuously supplied input data is divided into blocks, and the blocks are processed concurrently by being assigned to each processor in the system. This approach not only requires a simple interconnection network but also reduces the number of communications among the processors very much. The data dependency of the blocks to be processed concurrently brings on dependency problems between the processors in the system. A systematic scheduling method has been developed by using a processors which can be used efficiently, the methods for solving dependency problems between the processors are investigated. Implementation procedures and results for FIR, recursive (IIR), and adaptive filtering algorithms are illustrated.

• Proceedings of the Korean Society of Computer Information Conference
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• 2017.07a
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• pp.1-2
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• 2017

본 논문에서는 지휘무장통제체계(이하 CFCS) 소프트웨어의 성능 향상 기법으로 고성능 컴퓨팅(이하 HPC) 시스템 활용 기법을 제안한다. 이 기법으로 본 논문에서는 HPC 분야인 멀티코어 프로세서를 활용하는 방법을 제안한다. 복잡한 반복연산을 하는 작업이 많은 CFCS의 특정 SW모듈에 대해 멀티코어 프로세싱 아키텍처를 이용한 병렬처리를 적용하여 기존 순차처리 대비 작업실행시간을 단축함으로써 작업 응답시간을 상당히 줄일 수 있다. 본 논문에서는 CFCS 시험 환경의 일부 특정 SW모듈 상에서 기존의 순차처리 방식으로 수행한 연산 결과와 다중 처리 프로그래밍 API인 OpenMP를 적용하여 수행한 연산 결과를 비교하여 CFCS에서의 멀티코어 프로세싱이 체계 전반의 성능 향상 면에서 효율적으로 사용될 수 있음을 보인다.