• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.15-23
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• 2009

This paper presents a novel high-speed, low-complexity flexible 128/64-point $radix-2^4$ FFT/IFFT processor for the applications in high-throughput MIMO-OFDM systems. The high radix multi-path delay feed-back (MDF) FFT architecture provides a higher throughput rate and low hardware complexity by using a four-parallel data-path scheme. The proposed processor not only supports the operation of FFT/IFFT in 128-point and 64-point but can also provide a high data processing rate by using a four-parallel data-path scheme. Furthermore, the proposed design has a less hardware complexity compared with traditional 128/64-point FFT/IFFT processors. Our proposed processor has a high throughput rate of up to 560Msample/s at 140MHz while requiring much smaller hardware expenditure satisfying IEEE 802.11n standard requirements.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.2
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• pp.73-78
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• 2023

The dining philosophers problem(DPP) is that five philosophers sit around a round table and eat spaghetti(or noodles) together, where they must have a pair of chopsticks(two) on both sides of them to eat, and if all philosophers have one chopstick on the right, no one can eat because the deadlock occurs. Deadlocks are a problem that frequently occur in parallel systems, and most current operating systems(OS) cannot prevent it. This paper proposes a silver bullet that causes no deadlock in an OS where all processors of 2≤n≤∞ have multiple parallel processing capabilities. The proposed method is a group round-robin method in which ⌊n/2⌋ odd processors form a group and perform simultaneously, and shift right to the next processor when execution ends. The proposed method is to perform two times for even processors, three times for odd processors per one round-robin. If the proposed method is performed n times, even-numbered processors perform n/2 times and odd-numbered processors perform (n-1)/2-times.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2003.12a
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• pp.665-668
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• 2003

컴퓨터 바이러스 문제에 대한 해결 주체는 현재의 클라이언트 중심에서 서버 중심으로 옮겨가는 것이 바람직하다. 그러나 지금까지 나온 서버용 안티바이러스 엔진들은 기존의 클라이언트용 엔진에 대한 반복 구현적인 성격이 강했기에 서버 시스템 자체의 특성을 충분히 감안하지 못하고 있다. 본 논문에서는 대부분의 서버들이 다수의 CPU 가진 병렬처리 시스템임을 감안하여 이러한 특징을 반영하여 전체적인 시스템 효율성을 높이도록 새로운 안티바이러스 엔진을 설계한 후 현재 구현 중인 주요 연구 내용을 소개한다. 다중프로세서 시스템에서 실행되는 안티바이러스 엔진은 하나의 모니터링 모듈에 다수의 동등한 에이전트 엔진을 가지고 구성된다. 모니터링 모듈은 엔진의 설치와 동적 부하균형, 자동갱신 등의 일을 담당한다. 에이전트 엔진들은 안티바이러스 기능을 기반으로 다양한 실행패턴을 가질 수 있으며 이를 통하여 서버에서 수행되는 효율성을 높일 수 있게 해준다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.65-72
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• 2005

We can integrate more IP blocks on a silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processors. However, most of existing SoC buses have bottleneck in on-chip communication because of shared bus architectures, which result in the performance degradation of systems. In most cases, the performance of a multi-processor system is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of the processors. We propose an efficient SoC Network Architecture(SNA) using crossbar routers which provide a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels for multi-masters. According to the proposed architecture, we design a model system for the SNA. The proposed architecture has a better efficiency by $40\%$ than the AMBA AHB according to a simulation result.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.1
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• pp.57-68
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• 1993

In this paper, we describe a multiprocessor system using the HiPi bus with pended protocol and multiple cache memories, and evalute the performance of the multiprocessor system in terms of processor utilization for various cache coherence protocols. The HiPi bus is delveloped as the shared bus of TICOM II which is a main computer system to establish a nation-wide computing network in ETRI. The HiPi bus has high data transfer rate, but it doesn't allow cache-to-cache transfer. In order to evaluate the effect of cache-to-cache transfer upon the performance of system and to choose a best-performed protocol for HiPi bus, we simulate as follows: First, we analyze the performance of multiprocessor system with HiPi bus in terms of processor utilizatIOn through simulation. Each of cache coherence protocol is described by state transition diagram, and then the probability of each state is calculated by Markov steady state. The calculated probability of each state is used as input parameters of simulation, and modeling and simulation are implemented and performed by using SLAM II graphic symbols and language. Second, we propose the HiPi bus which supports cache-to-cache transfer, and analyze the performance of multiprocessor system with proposed HiPi bus in terms of processor utilization through simulation. Considered cache coherence protocols for the simulation are Write-through, Write-once, Berkely, Synapse, Illinois, Firefly, and Dragon.

• Aerospace Engineering and Technology
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• v.8 no.1
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• pp.172-178
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• 2009

Recently, autopilot is essential to reduce pilot's workload and increase flight safety. Avionics system of the small aircraft also has progressively adopted centralized multi-processor and multi-process computing architectures similar to the integrated modular avionics of B-777. It is increased more and more that importance of the flight control system. In this paper, the performance of the autopilot for the small aircraft has been verified with Hardware-In-the-Loop Simulation(HILS). Also, the autopilot algorithm that is operated in the Flight Control Computer(FCC) for the Fly by Wire(FBW) was verified with PILS and compared with the HILS results for the several commercial autopilots.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5A
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• pp.494-499
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• 2008

In this study, a Software Defined Radio(SDR) technology-based digital filtering technique applicable to a multiple channel processing system such as a wireless mobile communication system using Code Division Multiple Access(CDMA) technology is proposed. The technique includes a micro-processor to redesign Finite Impulse Response(FIR) filter coefficients according to specific system information and to download the filter coefficients to one digital Band Pass Filter(BPF) to reconfigure another system. The feasibility of the algorithm is verified by implementing a multiple channel signal generator that is reconfigurable to other system profiles, including those for a CDMA system and a WCDMA system on identical hardware platform.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.151-153
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• 1998

사용자 레벨 입출력은 유연성이 있고 효율적인 디바이스 드라이버를 만들 수 있게해주기 때문에, 내장 실시간 시스템에서 그 중요성이 더해가고 있다. 내장 실시간 시스템에서 사용자 레벨 입출력을 지원하기 위해서는 운영체제가 입출력 장치에서 발생한 외부 인터럽트를 프로세서에 예측 가능하고 효율적인 방법으로 전달할 수 있는 방법을 제공해야 한다. 본 논문에서는 새로운 사용자 레벨 시그널 처리 기법을 기반으로 한 효율적인 사용자 레벨 입출력 기법을 제안한다. 제안된 기법은 동적 가상 쓰레드 바인당(dynamic virtual binding)과 스케줄링 이벤트 업콜(scheduling event upcall)등의 다중 쓰레딩을 지원하기 위한 커널 구조를 이용하여 기존 시그널 처리의 문제점을 해결한다. 본 논문에서는 제안된 기법은 ARX실시간 운영체제상에 구현하여 그 성능을 측정하였다. 실험결과 제안된 기법은 적은 부하로 외부에서 발생한 인터럽트를 사용자 프로세서에 예측 가능한 시간에 전달한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.11a
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• pp.1283-1286
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• 2005

최근의 대용량 다중 분산 라우터 시스템은 다수의 라인 인터페이스 모듈들과 라우팅 처리 모듈, 스위칭 패브릭 모듈로 구성되어 있고, 고속의 패킷 스위칭 및 라우팅을 구현하기 위하여 일반적으로 입력 패킷을 외부로 전송하기 위한 기능과 제어 및 관리 기능을 담당하는 기능으로 분리하여 실행되고 있다. 이러한 라우터에서는 내부 모듈들의 프로세서들 사이에 정보 송수신을 위해 프로세서 간 통신(IPC : Interprocess Communication)이 이용되고 있다. 라우터의 기능 중 제어 및 관리 기능은 신속한 처리를 위하여 UDP/IP 방식의 IPC 가 사용되고 있는데, 이 UDP/IP 방식을 개선 방안을 제안하고 prototype 시스템을 구현하여 시험한 결과 라우터의 데이터 round trip 시간과 throughput 이 각각 15.1%, 4.3%의 개선되어 라우터의 성능이 향상되었다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.6
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• pp.19-24
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• 2004

A novel fast parallel NTGST is proposed for high resolution computer vision inspection of the BLUs in a LCD production line. The conventional computation- intensive NTGST algorithm is modified and its C codes are optimized into fast NTGST to be adapted to the SIMD parallel architecture. And then, the input inspection image is partitioned and allocated to each of the P processors in multi-threaded implementation, and the NTGST is executed on SIMD architecture of N data items simultaneously in each thread. Thus, the proposed inspection system can achieve the speedup of O(NP). Experiments using Dual-Pentium III processor with its MMX and extended MMX SIMD technology show that the proposed parallel NTGST is about Sp=8 times faster than the conventional NTGST, which shows the scalability of the proposed system implementation for the fast, high resolution computer vision inspection of the various sized BLUs in LCD production lines.