• Journal of Broadcast Engineering
• /
• v.16 no.2
• /
• pp.258-273
• /
• 2011

This paper designs and implements a multi-view 3D video player system which is operated faster than existing video player systems. The structure for obtaining the near optimum speed in a multi-processor environment by parallelizing the component modules is proposed to process large volumes of multi-view image data at high speed. In order to use the concurrency of bottleneck, we designed image decoding, synthesis and rendering modules in a pipeline structure. For load balancing, the decoder module is divided into the unit of viewpoint, and the image synthesis module is geometrically divided based on synthesized images. As a result of this experiment, multi-view images were correctly synthesized and the 3D sense could be felt when watching the images on the multi-view autostereoscopic display. The proposed application processing structure could be used to process large volumes of multi-view image data at high speed, using the multi-processors to their maximum capacity.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.6 s.348
• /
• pp.9-17
• /
• 2006

We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.

• Journal of Digital Convergence
• /
• v.17 no.8
• /
• pp.229-235
• /
• 2019

As the demand for broadband multimedia including the Internet explosively increases, the advancement of the subscriber network is becoming the biggest issue in the telecommunication industry due to the surge of data traffic caused by the emergence of new services such as smart phone, IPTV, VoIP, VOD and cloud services. In this paper, we have developed WDM(Wavelength Division Multiplexing)-PON(passive optical network) based on the 1-Gigabit Reach Externder (RE) technique to reduce optical core. Particularly, in order to strengthen the market competitiveness, we considered low cost, miniaturization, integration technique, and low power of optical parts. In addition, we have developed a batch system by integrating all techniques for reliability, remote management through the development of transmission distance extension and development of capacity increase of optical line by using RE technology in existing PON network. Based on system interworking with existing commercial 1G PON devices, it can be worthy of achievement of wide nationalization and optical core reduction by using this developed system. Based on these results, we are studying development of 10G PON technology.

• The KIPS Transactions:PartA
• /
• v.17A no.6
• /
• pp.275-280
• /
• 2010

In this paper, we discuss and propose an efficiently parallelized block cipher algorithm on the CELL BE processor. With considering the heterogeneous feature of the CELL BE architecture, we apply different encoding/decoding methods to PPE and SPE and improve the throughput. Our implementation was fully tested, with execution results showing achievement of high throughput, capable of supporting as high network speed as 2.59 Gbps. Compared to various parallel implementations on multi-core systems, our approach provides speedup of 1.34 in terms of encoding/decoding speed.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
• /
• v.30 no.2
• /
• pp.135-142
• /
• 2012

In the present study, a parallel processing method running on a multi-core PC-Cluster is introduced to produce digital surface model (DSM) and digital terrain model (DTM) from huge airborne laser scanning data. A hybrid model using both message passing interface (MPI) and OpenMP was devised by revising a conventional MPI model which utilizes only MPI, and tested on a multi-core PC-Cluster for performance validation. In the results, the hybrid model has not shown better performances in the interpolation process to produce DSM, but the overall performance has turned out to be better by the help of reduced MPI calls. Additionally, scheduling function of OpenMP has revealed its ability to enhance the performance by controlling inequal overloads charged on cores induced by irregular distribution of airborne laser scanning data.

• Journal of Advanced Navigation Technology
• /
• v.25 no.4
• /
• pp.293-298
• /
• 2021

In general, the guided weapon seeker and the guided control device process the target, search, recognition, and capture information to indicate the state of the guided missile, and play a role in controlling the operation and control of the guided weapon. The signals required for guided weapons are gaze change rate, visual signal, and end-stage fuselage orientation signal. In order to process the complex and difficult-to-process missile signals of recent missiles in real time, it is necessary to increase the data processing speed of the missiles. This study showed the processing speed after applying the stop and go and inverse enumeration algorithm among the parallel algorithm methods of PINQ and comparing the processing speed of the signal data required for the guided missile in real time using the guided missile inspection program. Based on the derived data processing results, we propose an effective method for processing missile data when applying a parallel processing algorithm by comparing the processing speed of the multi-core processing method and the single-core processing method, and the CPU core utilization rate.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.40 no.11
• /
• pp.972-978
• /
• 2012

This paper discusses the parallelization of multifrontal solution method, widely used for finite element structural analyses, for a shared memory architecture. Multifrontal method is easier than other linear solution methods because the solution procedure implies that unknowns can be eliminated simultaneously. Two innovative ideas are introduced to achieve optimal solver performance on a shared memory computer. Those are pairing two frontal matrices and splitting the frontal matrix in order to reduce the temporal memory space required by independent computing tasks. Performance comparisons between original algorithm and proposed one prove that proposed method is more computationally efficient on current multicore machines.

• Journal of the Korea Society of Computer and Information
• /
• v.16 no.1
• /
• pp.1-9
• /
• 2011

Recently, as mobile multimedia devices are used more and more, the needs for high-performance and low-energy multimedia processors are increasing. Application-specific integrated circuits (ASIC) can meet the needed high performance for mobile multimedia, but they provide limited, if any, generality needed for various application requirements. DSP based systems can used for various types of applications due to their generality, but they require higher cost and energy consumption as well as less performance than ASICs. To solve this problem, this paper proposes a single instruction multiple data (SIMD) based many-core processor which supports high-performance and low-power image data processing while keeping generality. The proposed SIMD based many-core processor composed of 16 processing elements (PEs) exploits large data parallelism inherent in image data processing. Experimental results indicate that the proposed SIMD-based many-core processor higher performance (22 times better), energy efficiency (7 times better), and area efficiency (3 times better) than conversional commercial high-performance processors.

• Proceedings of the KIPE Conference
• /
• 2015.07a
• /
• pp.528-529
• /
• 2015

본 논문은 DC-DC 플라이백 컨버터 회로를 바탕으로, 고전압 입력으로부터 다채널의 절연된 저전압을 출력하는 고압 SMPS에 관한 것이다. 제안된 토폴로지는 고전압을 분배하는 커패시터와 MCU 전용의 커패시터를 직렬로 구성하고, 각 커패시터에 분배된 전압을 입력으로 다중여자 방식의 플라이백 컨버터 구조로 되어있다. 직렬 커패시터 구조는 고압환경에서의 소자들의 절연 및 전압스트레스를 저감할 수 있으며, MCU 전용의 커패시터는 시스템의 초기구동을 위한 자가충전(Self-Power) 및 Black-Start의 시스템 안정화 구조이다. 또한 다중여자방식은 변압기의 단일 코어를 사용하여 스위칭 전류를 흘려줌으로서 커패시터의 전압불균형을 막을 수 있는 장점을 가지고 있다. 제안된 토폴로지는 시뮬레이션을 통하여 타당성을 검증하였다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2010.11a
• /
• pp.596-598
• /
• 2010

본 논문에서는 의료영상 중 X-ray 영상을 대상으로 영상을 분류하고 분류 결과에 따라 다중 키워드를 생성하는 방법을 제시한다. X-ray영상은 대부분 그레이 영상임으로 Local Binary Patterns (LBP)을 이용하여 픽셀간의 연관성을 특징으로 추출하고, 실시간 학습 및 분류가 가능한 Random Forests 분류기로 영상들을 30개의 클래스로 분류한다. 또한, 미리 정의된 신체 부위간의 관계 가중치를 분류 스코어에 결합하여 신뢰값을 생성하고 이를 기반으로 영상에 대해 다중 주석을 부여하게 된다. 이렇게 부여된 다중 주석은 키워드 기반의 의료영상을 가능케 함으로 보다 쉽고 효율적인 검색 환경을 제공할 수 있다.