• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.123-134
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• 2000

This paper addresses a new triangulation method for constructing surface model from a set of wire-frame contours. The most important problem of contour triangulation is the branching problem, and we provide a new solution for the double branching problem, which occurs frequently in real data. The multiple branching problem is treated as a set of double branchings and an algorithm based on contour merging is developed. Our double branching algorithm is based on partitioning of root contour by Toussiant's polygon triangulation algorithml[14]. Our double branching algorithm produces quite natural surface model even if the branch contours are very complicate in shape. We treat the multiple branching problem as a problem of coarse section sampling in z-direction, and provide a new multiple branching algorithm which iteratively merge a pair of branch contours using imaginary interpolating contours. Our method is a natural and systematic solution for the general branching problem of contour triangulation. The result shows that our method works well even though there are many complicated branches in the object.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.5
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• pp.297-305
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• 2006

Trace-driven simulation is widely used for measuring the performance of a microprocessor in its initial design phase. However, since it requires much time and disk space, the statistical simulation has been studied as an alternative method. In this paper, statistical simulations are performed for a high performance superscalar microprocessor with a perceptron-based multiple branch predictor. For the verification, various hardware configurations are simulated using SPEC2000 benchmarks programs as input. As a result, we show that the statistical simulation is quite accurate and time saving for the evaluation of microprocessor architectures with multiple branch prediction.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.13-15
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• 2001

최근에 이르러 프로세서의 병렬성을 분석적 기법으로 예측하기 위한 연구가 활발해지면서 프로세서의 성능 예측 모델에 대한중요성이 대두되고 있다. 그러나 기존의 연구는 현재 광범위하게 사용되고 있는 다중 분기 예측법을 이용하는 프로세서에 대하여 분기 차수와 관계없는 재귀적 성능 모델을 제공해주지 않는다. 본 논문에서는 이것을 해결하기 위하여, 매 싸이클마다 명령어 종속 트리를 구성하고 종속인 명령어 간에 상대적인 병렬도 갓을 부여하여 성능 예측 모델 입력 데이타를 측정하였다. 그 곁과, 다중 분기 예측법을 사용하는 프로세서에서 정수형 프로그램에 대한 성능을 기존의 성능모델보다 작은 상대 오차로 예측할 수 있다.

• ETRI Journal
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• v.11 no.2
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• pp.51-63
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• 1989

본고에서는 융통성있고 경제적인 디지틀 통신망 구성에 필수적으로 소요되는 망노드에서의 디지틀 다중 및 회선 분기/분배 기술에 대하여 살펴보고 미래의 동기식 전송망에서 핵심이 될 광대역 회선 분기/분배 기술을 실현하기 위한 장치의 구성 방안, 동기 방식, 소요 기능 요구사항, 그리고 응용영역에 대해 고찰하였다.

• The KIPS Transactions:PartB
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• v.14B no.6
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• pp.413-422
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• 2007

This paper addresses a new technique for constructing surface model from a set of wire-frame contours. The most difficult problem of this technique, called contour triangulation, arises when there are many branches on the surface, and causes lots of ambiguities in surface definition process. In this paper, the branching problem is reduced as the surface reconstruction from a set of virtual belts and virtual canyons. To tile the virtual belts, a divide-and-conquer strategy based tiling technique, called the BPA algorithm, is adopted. The virtual canyons are covered naturally by an iterative convex removal algorithm with addition of a center vertex for each branching surface. Compared with most of the previous works reducing the multiple branching problem into a set of tiling problems between contours, our method can handle the problem more easily by transforming it into more simple topology, the virtual belt and the virtual canyon. Furthermore, the proposed method does not involve any set of complicated criteria, and provides a simple and robust algorithm for surface triangulation. The result shows that our method works well even though there are many complicated branches in the object.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.245-246
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• 2008

변전소 모선에서 측정되는 전압, 전류를 기반으로 하는 CB기반 고장거리 추정기법은 배전선의 다중 분기선 때문에 다중개의 고장위치를 추론하는 것은 물론 분기 부하모델의 불확실성으로 인해 거리 계산에 오차를 포함하게 된다. 따라서 본 연구에서는 유비쿼터스 기반의 배전계통 하에서 구간 측정 전압, 전류 및 IED간 정보교환을 통해 얻어지는 전압, 전류 정보를 이용하여 고장경로를 추정하는 IED 기반 고장경로 추정기법을 제안한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1551-1558
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• 2022

We propose a two-tier cooperative computing system comprised of a mobile device and an edge server for partial offloading of multi-branch structures in Fog/Edge Computing environments in this paper. The proposed system includes an algorithm for splitting up application service processing by using reconstructive linearization techniques for multi-branch structures, as well as an optimal collaboration algorithm based on partial offloading between mobile device and edge server. Furthermore, we formulate computation offloading and CNN layer scheduling as latency minimization problems and simulate the effectiveness of the proposed system. As a result of the experiment, the proposed algorithm is suitable for both DAG and chain topology, adapts well to different network conditions, and provides efficient task processing strategies and processing time when compared to local or edge-only executions. Furthermore, the proposed system can be used to conduct research on the optimization of the model for the optimal execution of application services on mobile devices and the efficient distribution of edge resource workloads.

• Korean Journal of Optics and Photonics
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• v.8 no.4
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• pp.340-344
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• 1997

We proposed and demonstrated a tunable wavelength optical add/drop multiplexer(OADM) employing piezoactuated fiber grating pairs and polarization beam splitters. We used piezostack act as a fiber stretcher, using the fact that the resonant wavelength of the grating can be controlled by the axial strain along the fiber grating. The polarization controlled configuration showed high stability because the reflected signals from the two identical gratings are dropped or added not by interference but by polarizations of the beams. We could add and drop not noly 1549.3nm signal channel(original gratings), but also 1550.1nm(tuned gratings) with PZT actuators and in both cases, we found that the rejection of adjacent channels was more than -26dB, and signal leakage at the gratings was less than -34dB.

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.4
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• pp.21-27
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• 1975

In this paper, a procedure for deriving of multiple fault detection test sets is presented for fan-out reconvergent combinational logic networks. A fan-out network is decomposed into a set of fan-out free subnetworks by breaking the internal fan-out points, and the minimal detecting test sets for each subnetwork are found separately. And then, the compatible tests amonng each test set are combined maximally into composite tests to generate primary input binary vectors. The technique for generating minimal test experiments which cover all the possible faults is illustrated in detail by examples.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.61-71
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• 2007

The instruction level parallelism, which has been used to improve the performance of processors, expose its limit. The change of a control flow by a branch miss prediction is one of the obstacles that restrict the instruction level parallelism. The single chip multiprocessors have been developed to utilize the thread level parallelism. However, we could not use the maximum performance of the single chip multiprocessor in case of executing the coded programs without considering the multi-thread. In order to overcome the two performance degradation factors, in this paper, we suggest the concurrent branch execution method that applies to the multi-path execution method at a single chip multiprocessor. We executes all two flows of the conditional branch using the idle core processor. Through this, we can improve the processor's efficiency with blocking the control flow termination by the branch instruction and reducing the idle time. We analyze the effects of concurrent branch execution proposed in this paper through the simulation. As a result of that, concurrent branch execution reduces about 20% of idle time and improves the maximum 10% of the branch prediction accuracy. We show that our scheme improves the overall performance of maximum 39% compared to the normal single chip multiprocessor and maximum 27% compared to the superscalar processor.