• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.11
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• pp.3227-3233
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• 2009

A method for performing Boolean resubstitution is proposed. This method is efficiently implemented using division matrix. It begins by creating an algebraic division matrix from given two logic expressions. By introducing Boolean properties and adding literals into the algebraic division matrix, we make the Boolean division matrix. Using this extended division matrix, Boolean substituted expressions are found. Experimental results show the improvements in the literal counts over well-known logic synthesis tools for some benchmark circuits.

• The Magazine of the IEIE
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• v.25 no.11
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• pp.42-50
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• 1998

시스템을 단일 칩에 구현함에 따라서 반도체 칩은 수백만 게이트를 내장할 정도로 고집적화 되어가고 있다. 이러한 고집적도의 칩을 제장하는 데 소요되는 고가의 텍스트비용을 최소화하기 위해 설계의 각 단계 별로 다양한 테스트설계기술이 개발되고 있다. 합성 후 회로구조가 테스트에 용이하도록 하기 위하여 상위 및 논리 합성 단계에서 테스트기능을 추가하고 있다. 합성된 회로에 대하여는 스캔 테스트점 삽입, 및 BIST 등의 테스트설계 기술이 사용되고 있다. 본 논문에서는 VHDLDD등으로 기술되는 상위 기능정보와 상위 구조합성과정에서 고려되고 이는 다양한 데스트합성 기술을 소개하고자 한다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.7
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• pp.3251-3257
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• 2011

This paper presents a new Boolean extraction technique for logic synthesis. This method extracts kernel-kernel pairs as well as cokernel-kernel pairs. The given logic expressions can be translated into Boolean divisors and quotients with kernel-kernel pairs. Next, kernel intersection method provides the common sub-expressions for several logic expressions. Experimental results show the improvement in literal count over previous other extraction methods.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1935_1936
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• 2009

기울기 S=2인 톱니맵 $S_2$(x) 와 텐트맵 $S_2$(x), 두 혼돈맵들을 차례로 연결시킨 합성맵을 사용하여 합성상태머신을 설계하였다. 혼돈맵의 합성논리를 이용하여 설계한 합성상태머신에서 발생하는 난수적인 상태들을 그래프적으로 보였으며, 난수적인 상태들의 주기는 정밀도와 이산화된 진리표에 따른 길이를 발생시켰다.

• Journal of the Korean Institute of Gas
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• v.5 no.1
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• pp.37-44
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• 2001

OPS(Operating Procedure Synthesis) systems can reduce the time and effort involved in OPS, make the analysis more thorough and detailed, and minimize or eliminate human errors. And OPS systems capture the expertise needed to create operating procedures and allow this experience to be used in the new situations. But there are the limitations of the OPS techniques that have been used. So in order to resolve this Problem, in this work we have proposed a new approach to utilize temporal constraints and specific process knowledge in temporal logic and description logic. We have demonstrated its remarkable effectiveness in a boiler plant.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.351-362
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• 2002

Along with an asynchronous finite state machine, in short AFSM, a signal transition graph, in short STG, is one of the most widely used behavioral description languages for asynchronous controllers. Unfortunately, STGs are not user-friendly, and thus it is very unwieldy and time consuming for system designers to conceive and describe manually the behaviors of a number of asynchronous controllers which constitute an asynchronous control unit for a target system in the form of STGs. In this paper, we suggest an automatic STG derivation method through a process-oriented method. Since the suggested method considers special properties of STG-based asynchronous logic synthesis very carefully, asynchronous controllers which are synthesized from STGs derived through the suggested method are superior in aspects of area, synthesis time, performance and implementability compared to those obtained through previous methods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2330-2336
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• 2013

Since many man-made systems consist of autonomous and interactive components, it is intrinsically difficult to analyze their abnormal behavior. The logical analysis of such a system is an indispensable process for high quality and reliable system development. In this paper, we propose an analysis method using two algebraic operations, named composition and minimization. Repetitive composition and minimization of component models with respect to a set of important events produces a new analysis model that has the same input output responses to an environment. An analysis example of the alternating bit protocol demonstrates the effectiveness of the proposed method showing that each message generated at the sender side eventually arrives to a receiver.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.8
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• pp.3715-3722
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• 2011

This paper presents a new Boolean extraction technique for logic synthesis. This method first calculates divisor/2-cube quotients, 2-cube quotient pairs, and 2-cube quotient matrices. Then we find candidates, which can be common sub-expressions, from 2-cube quotients and matrices. Next, candidate intersection provides the common sub-expressions for several logic expressions. Experimental results show the improvements in literal counts over the previous methods.

• Journal of Advanced Navigation Technology
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• v.16 no.1
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• pp.62-69
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• 2012

Multiple-control Toffoli(MCT) gates are macro-level multiple-valued gates needing quantum technology dependent primitive gates, and have been used in Galois Field sum-of-product (GFSOP) based synthesis of quantum logic circuit. Reversible logic is very important in quantum computing for low-power circuit design. This paper presents a reversible GF4 multiplier at first, and GF4 multiplier based quaternary MCT gate realization is also proposed. In the comparisons of MCT gate realization, we show the proposed MCT gate can reduce considerably primitive gates and delays in contrast to the composite one of the smaller MCT gates in proportion to the multiple-control input increase.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.3
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• pp.134-142
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• 2005

The implementation of Multiple-Valued Logic(MVL) based on Current-Mode CMOS Logic(CMCL) circuits has recently been achieved. In this paper, four-valued Unary Multiple-Valued logic functions are synthesized using current-mode CMOS logic circuits. We properly make use of the fact that the CMCL addition of logic values represented using discrete current values can be performed at no cost and that negative logic values are readily available via reversing the direction of current flow. A synthesis process for CMCL circuits is based upon a logically complete set of basic elements. Proposed algorithm results in less expensive realization than those achieved using existing techniques in terms of the number of transistors needed. As an alternative to the cost-table techniques Universal Unary Programmable Circuit (UUPC) for a unary function is also proposed.