• Title/Summary/Keyword: 네트워크 슬라이스

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VLSI Architecture for High Speed Implementation of Elliptic Curve Cryptographic Systems (타원곡선 암호 시스템의 고속 구현을 위한 VLSI 구조)

  • Kim, Chang-Hoon
    • The KIPS Transactions:PartC
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    • v.15C no.2
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    • pp.133-140
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    • 2008
  • In this paper, we propose a high performance elliptic curve cryptographic processor over $GF(2^{163})$. The proposed architecture is based on a modified Lopez-Dahab elliptic curve point multiplication algorithm and uses Gaussian normal basis for $GF(2^{163})$ field arithmetic. To achieve a high throughput rates, we design two new word-level arithmetic units over $GF(2^{163})$ and derive a parallelized elliptic curve point doubling and point addition algorithm with uniform addressing based on the Lopez-Dahab method. We implement our design using Xilinx XC4VLX80 FPGA device which uses 24,263 slices and has a maximum frequency of 143MHz. Our design is roughly 4.8 times faster with 2 times increased hardware complexity compared with the previous hardware implementation proposed by Shu. et. al. Therefore, the proposed elliptic curve cryptographic processor is well suited to elliptic curve cryptosystems requiring high throughput rates such as network processors and web servers.

A Traffic Pattern Matching Hardware for a Contents Security System (콘텐츠 보안 시스템용 트래픽 패턴 매칭 하드웨어)

  • Choi, Young;Hong, Eun-Kyung;Kim, Tae-Wan;Paek, Seung-Tae;Choi, Il-Hoon;Oh, Hyeong-Cheol
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.46 no.1
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    • pp.88-95
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    • 2009
  • This paper presents a traffic pattern matching hardware that can be used in high performance network applications. The presented hardware is designed for a contents security system which is to block various kinds of information drain or intrusion activities. The hardware consists of two parts: the header lookup and string pattern matching parts. For implementing the header lookup part in hardware, the TCAMs(ternary CAMs) are popularly used. Since the TCAM approach is inefficient in terms of the hardware and memory costs and the power consumption, however, we adopt and modify an alternative approach based on the comparator arrays and the HiCuts tree. Our implementation results, using Xilinx FPGA XC4VSX55, show that our design can reduce the usage of the FPGA slices by about 26%, and the Block RAM by about 58%. In the design of string pattern matching part, we design and use a hashing module based on cellular automata, which is hardware efficient and consumes less power by adaptively changing its configuration to reduce the collision rates.