• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.152-152
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• 2011

Silicon 기반의 환경에서 연구 및 제조되는 전자소자는 반도체의 기술이 발전함에 따라 chip 선폭의 크기가 30 nm에서 20 nm, 그리고 그 이하의 크기로 점점 더 작아지는 요구에 직면하고 있다. 탄소나노 구조와 나노와이어 기술이 Silicon을 대신할 다음세대 기술로 주목받고 있다. 많은 연구결과들 중에서 III-V CMOS가 가장 빠른 접근 방법이라 예상한다. III-V족 물질을 이용하면 electron 보다 수십 배 이상의 이동도를 얻을 수 있으나 p-type의 구조를 구현하는 것이 해결해야 할 문제이다. p-type 3-5 족 화합물을 이용하여 에너지 밴드 갭의 변화를 가능하게 한다면 hole의 이동도를 크게 향상시킬 수 있어 silicon 기반의 p-type 소자보다 2~3배 더 빠른 소자의 구현이 가능하다. 3-5족 화합물 반도체의 성장 기술이 많이 진보되어 이를 이용하여 고속 소자를 구현한다면 시기적으로 더욱 빨리 다가올 것이라 예측한다. 에너지 밴드갭의 변화와 격자 부정합을 고려하여 SI InP 기판에 GaSb 물질을 채널로 사용한 p-type 2-dimensional hole gas (2DHG) 소자를 구현하였다. 관찰된 소자 구조의 박막 상태의 특징을 보이며 10 um ${\times}$ 10 um AFM 측정결과 1 nm 이하의 표면 거칠기를 가지며 상온에서의 hole 이동도는 약 650 cm2/Vs이고 sheet carrier density는 $5{\times}1012$ /cm2의 결과를 확인하였다. 실험결과 InP 기판위에 채널로 사용된 GaSb 박막을 올리는데 있어 가장 중요한 것은 Phosphorus, Arsenic, 그리고 Antimony 물질의 양과 이들의 변화시간의 조절이다. 본 발표에서 Semi-insulating InP 기판위에 electron이 아닌 hole을 반송자로 이용한 차세대 고속 전자소자를 구현하고자 하여 MBE (Molecular Beam Epitaxy)로 p-type 소자를 구현하여 실험하였다. 아울러 더욱 빠른 소자의 구현을 위하여 세계의 유수 그룹들의 연구 결과들과 앞으로 예상되는 고속 소자에 대해서 비교와 함께 많은 기술에 대해 논의하고자 한다.

• Journal of IKEEE
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• v.22 no.1
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• pp.74-79
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• 2018

We analyzed the relationship between center potential and subthreshold swing (SS) of Junctionless Cylindrical Surrounding Gate (JLCSG) and Junctionless Double Gate (JLDG) MOSFET. The SS was obtained using the analytical potential distribution and the center potential, and SSs were compared and investigated according to the change of channel dimension. As a result, we observed that the change in central potential distribution directly affects the SS. As the channel thickness and oxide thickness increased, the SS increased more sensitively in JLDG. Therefore, it was found that JLCSG structure is more effective to reduce the short channel effect of the nano MOSFET.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.302-302
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• 2012

최근 비 휘발성 메모리 시장의 확대와 수요가 많아지면서, 비휘발성 메모리 소자의 제작에 대한 연구가 활발히 진행되고 있다. 특히, 실리사이드 나노입자를 적용한 소자는 현 실리콘 기반의 반도체 공정의 적용이 용이하다. 따라서 본 연구에서는 실리사이드 계열의 화합물 중에서 일함수가 4.63 eV인 Vanadium silicide (V3Si) 나노입자 메모리소자를 제작하여 전기적 특성과 열 안정성에 대하여 알아보았다. p-Si기판에 약 6nm 두께의 SiO2 터널층을 건식 산화 방법으로 성장시킨 후 V3Si 나노입자를 제작하기 위해서 V3Si 금속박막을 스퍼터링 방법으로 4 nm~6 nm의 두께로 터널 절연막 위에 증착시켰다. 그리고 컨트롤 절연막으로 SiO2를 초고진공 스퍼터를 이용하여 50 nm 증착하였고, 급속 열처리 방법으로 질소 분위기에서 $800^{\circ}C$의 5초 동안 열처리하여 V3Si 나노 입자를 형성하였다. 마지막으로 200 nm두께의 Al을 증착하고, 리소그래피 공정을 통하여 채널 길이와 너비가 각각 $2{\mu}m$, $5{\mu}m$, $10{\mu}m$를 가지는 트랜지스터를 제작하였다. 제작된 시편의 V3Si 나노입자의 크기와 균일성은 투과 전자 현미경으로 확인하였고, 후 열처리 공정 이후 V3Si의 존재여부의 확인을 위해서 X-ray 광전자 분광법의 표면분석기술을 이용하여 확인하였다. 소자의 전기적인 측정은 Agilent E4980A LCR meter, 1-MHz HP4280A와 HP 8166A pulse generator, HP4156A precision semiconductor parameter analyzer을 이용하여 측정온도를 $125^{\circ}C$까지 변화시키면서 전기적인 특성을 확인하였다. 본 연구에서는 온도에 선형적 의존성을 가지는 전하누설 모델인 T-model 을 이용하여 나노입자 비휘발성 메모리소자의 전하누설 근원을 확인한 후, 메모리 소자의 동작 특성과의 물리적인 연관성을 논의하였다. 이를 바탕으로 나노입자 비휘발성 메모리소자의 열적안정성을 확보하고 소자 특성향상을 위한 최적화 구조를 제안하고자 한다.

• Composites Research
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• v.36 no.3
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• pp.217-223
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• 2023

In this work, the preparation and its oil adsorption behavior of polyacrylonitrile-based carbon nanofiber sponge were investigated. The prepared carbon sponges showed excellent selective oil adsorption in the mixture of water and oil, and the adsorption capacity of reused carbon nanofiber sponge was also investigated. Further, carbon nanofiber sponge adsorbent with internally structured channel showed fast oil adsorption behavior due to a capillary phenomenon. After use, sponge adsorbent was heat-treated at 800℃ under N² and studied the possibility of a sensor for electrochemical detection of 4-aminophenol.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.479-485
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• 2006

The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin undoped Si channel for SCEs control, ale being validated for sub-20nm scaling. A novel analytical transport model for the subthreshold mode of DGMOSFETs is proposed in this paper. The model enables analysis of short channel effect such as the subthreshold swing(SS), the threshold voltage roil-off$({\Delta}V_{th})$ and the drain induced barrier lowering(DIBL). The proposed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. An approximative solution of the 2D Poisson equation is used for the distribution of electric potential, and Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The new model is used to investigate the subthreshold characteristics of a double gate MOSFET having the gate length in the nanometer range $(5-20{\sim}nm)$ with ultra thin gate oxide and channel thickness. The model is verified by comparing the subthreshold swing and the threshold voltage roll-off with 2D numerical simulations. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.31 no.1 s.256
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• pp.50-54
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• 2007

Nickel nano and microstructures are fabricated with simple process. The fabrication process consists of nickel deposition, lithography, nickel ion etching and plasma ashing. Well-aligned nickel nanowalls and nickel self-encapsulated microchannels were fabricated. We found that the ion etching condition as a key fabrication process of nickel nanowalls and self-encapsulated microchannels, i.e., 40 sccm Ar flow, 550 W RF power, 15 mTorr working pressure, and $20^{\circ}C$ water cooled platen without using He backside cooling unit and with using it, respectively. We present the experimental results and discuss the formational conditions and the effect of nickel redeposition on the fabrication of nickel nano and microstructures.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.869-872
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• 2006

In this paper, the threshold voltage roll-off been analyzed for nano structure double gate FinFET. The analytical current model has been developed , including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics are used to calculate thermionic emission current, and WKB(Wentzel- framers-Brillouin) approximation to tunneling current. The threshold voltage roll-offs are obtained by simple adding two currents since two current is independent. The threshold voltage roll-off by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the threshold voltage roll-off Is very large. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects and this process has to be developed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.760-765
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• 2007

In this paper, the threshold voltage roll-off and drain induced barrier lowering(DIBL) have been analyzed for nano structure double gate FinFET. The analytical current model has been developed, including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics were used to calculate thermionic omission current, and WKB(Wentzel- Kramers-Brillouin) approximation to tunneling current. The threshold voltage roll-offs are obtained by simple adding two currents since two current is independent. The threshold voltage roll-off by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the threshold voltage roll-off and DIBL are very large. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects, and this process has to be developed.

• Membrane Journal
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• v.26 no.6
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• pp.421-431
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• 2016

Novel membrane technologies that harness ordered nanostructures have recently received much attention because they allow for high permeability due to their reduced flow resistance while also maintaining high selectivity due to their isoporous characteristics. In particular, the opaline structure (made from the self-assembly of colloidal particles) and its inverted form (inverse-opal) have shown strong potential for membrane applications on account of several advantages in processing and the resulting membrane properties. These include controllability over the pore size and surface functional moieties, which enable a wide range of applications ranging from size-exclusive separation to catalytically-reactive membranes. Furthermore, when combined with multiscale architecturing strategies, inverse-opal-structured membranes can be designed to have specific pores or channel structures. These materials are anticipated to be utilized for next-generation, high-performance, and high-value-added functional membranes. In this review article, various types of inverse-opal-structured membranes are reviewed and their functionalization through hierarchical structuring will be comprehensively investigated and discussed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.715-717
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• 2010

In this paper, the subthreshold characteristics have been alanyzed using MicroTec4.0 for double gate MOSFET(DGMOSFET). The DGMOSFET is extensively been studing since it can reduce the short channel effects due to structural characteristics. We have presented the short channel effects such as subthreshold swing and threshold voltage for DGMOSFET, using MicroTec, semiconductor simulator. We have analyzed for channel length, thickness and width to consider the structural characteristics for DGMOSFET. The subthreshold swing and threshold voltage have been analyzed for DGMOSFET using MicroTec since MicroTec is well verified as comparing with results of the numerical three dimensional models.