• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.264-265
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• 2013

현재 반도체 산업에서는 고성능 저전력과 더불어 고 집적도가 가능한 재료 및 구조에 크게 주목하고 있고 여러 가지 이슈를 만족시키기 위해서 다양한 재료와 구조가 많이 연구 되고 있다. 특히 3-5족 화합물로 만들어진 나노선은 소자의 미세한 구조적 제어를 가능하게 하고 1차원 구조적 특성에 의해 전기적 특성이 우수하여 전계효과 트랜지스터(FET) 소자에 적용 시키기 적합하다고 알려져 있다.[1,2] 이번 연구에서는 최근 많이 연구되고 있는 GaAs 나노선을 기반으로 하는 전계효과 트랜지스터의 소자특성 및 전기적인 특성에 대해 EDISON 시뮬레이터를 이용해 알아보았다. 또한 채널 두께 및 길이와 게이트 산화막 층 두께에 따른 소자의 전기적 특성에 대해서도 연구하였다. 이를 통해 GaAs 나노선 기반 전계효과 트랜지스터의 최적화된 소자를 알아 보았다.

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.75-88
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• 2014

본 연구에서는 비선형 Poisson-Boltzmann 식의 해를 구할 수 있는 웹 기반 EPBS를 이용하여 이온채널의 전하 분포와 유전률이 이온채널의 이온선택성에 미치는 영향에 대해 알아본다. 모델로 사용한 이온채널은 이온채널과 유사한 구조를 갖는 합성 단백질인 고리형 펩타이드 나노튜브와 자연계에 존재하는 Gramicidin A 이다. 계산 결과로부터 용매인 물과 단백질의 유전율 차이에 의해 이온이 이온채널을 통과할 때 반응장이 생성되며, 이는 이온과 상호작용을 통해 이온 종류에 관계없이 이온 통과를 방해하는 에너지 장벽을 형성함을 알 수 있다. 한편, 두 이온채널 부분 전하, 특히 골격에 존재하는 카르보닐기의 쌍극자 모멘트에 의해 이온채널 내부에는 0 보다 작은 정전기 퍼텐셜이 형성된다. 이온채널 내부의 총 정전기 퍼텐셜은 이온채널의 부분 전하에 의한 정전기 퍼텐셜과 유전률 차이에 의한 반응장의 합으로 나타나며, 계산 결과 0 보다 작은 값을 갖는다. 이로부터 본 연구에서 사용된 두 종류의 이온채널이 양이온에 선택성이 있음을 알 수 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.109-114
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• 2002

In this paper, we have presented the simulation results ah)ut threshold voltage for Si-based MOSFETs with channel length of nano scale. We simulated the Si-based n channel MOSFETs with gate lengths from 180 to 30 nm in accordance to the constant voltage scaling theory and the lateral scaling. These MOSFETs had the lightly doped drain(LDD) structure, which is used for the reduction of electric field magnitude and short channel effects at the drain region. The stronger electric field at this region is due to scaling down. We investigated and analyzed the threshold voltage of these devices. This analysis will provide insight into some applicable limitations at the ICs and used for basis data at VLSI.

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.89-101
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• 2014

나노 규모의 좁은 공간에서는 분자들과 벽면과의 상호작용이 커서 분자들의 거동에 큰 영향을 준다. 이와 관련하여 최근에 나노슬릿 (nano-slit)이나 나노채널(nano-channel)과 같은 제한된 공간(confined geometry)에서 DNA의 구조적, 동역학적 거동에 관한 연구가 활발히 진행 중이다. 이러한 연구에서 모티브를 얻어 많은 입자들(spheres)로 이루어진 나노슬릿(nano-slit)사이에 Leonard-Jones potential을 따르는 용매분자들과 고분자가 들어있는 시스템을 구성하여 고분자의 동역학에 관해 연구하고자 하였다. 이때 슬릿(slit)은 약간의 탄성 포텐셜을 가지는 경우와 완전히 고정되어서 움직이지 않는 경우로 나누어 실행하였다. 더불어 고분자의크기, 용매의 종류, slit 사이의 간격 등의 변화가 고분자의 동역학에 어떤 영향을 주는지 살펴보았다. 이를 통해 환경적 조건에 따른 나노슬릿(nano-slit)에서 고분자의 움직임의 양상을 이해할 수 있었다.

• Journal of the Korean Electrochemical Society
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• v.24 no.1
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• pp.7-12
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• 2021

In this study, we investigated the formation of the metal oxide nanostructure by anodization of aluminum 3104H18 alloy. The anodization was performed in pyrophosphoric acid (H4P2O7) electrolyte. By the control of anodization condition such as concentration of electrolyte, anodization temperature and applied voltage, nanoporous or nanofiber structures were obtained. The optimal anodization condition to form nanofiber structures are 75 wt% of H4P2O7 at 30 V and 20℃. When anodization was performed at over 40 V, nanoporous structures were formed due to accelerated dissolution reaction rate of nanofiber structures or increasing thickness of channel wall.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.317-320
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• 2001

In this paper, we have presented the simulation results about threshold voltage at Si-based MOSFETs with channel length of nano scale. We simulated the Si-based n-channel MOSFETS with sate lengthes from 180 to 30 nm in accordance to constant voltage scaling theory. These MOSFETs had the lightly doped drain(LDD) structure, which is used for the reduction of electric field magnitude and short channel effects at the drain region. The stronger electric field at this region it due to scaling down. We investigated and analysed the threshold voltage of these devices. This analysis will provide insight into some applicable limitations at the ICs and used for basis data at VLSI.

• Journal of IKEEE
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• v.13 no.2
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• pp.126-131
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• 2009

To overcome short channel effects, wrap-around field effect transistors have drawn a great deal of attention for their superior electrostatic coupling between the channel and the surrounding gate electrode. In this paper, we introduce a bottom-up technique to fabricate a wrap-around field effect transistor using silicon nanowires as the conduction channel. Device fabrication was consisted mainly of electron-beam lithography, dielectrophoresis to accurately align the nanowires, and the formation of gate electrode using electrochemical deposition. The electrolyte for electrochemical deposition was made up of non-toxic organic-based solution and liquid nitrogen was used as a method of maintaining the shape of polymethyl methacrylate(PMMA) during the process of electrochemical deposition. Patterned PMMA can be used as a nano-template to produce wrap-around gate nano-structures.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.41 no.6
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• pp.429-434
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• 2017

A molecular-continuum hybrid method was developed to simulate microscale and nanoscale fluids where continuum fluidics cannot be used to predict Couette flow. Molecular dynamics simulation is used near the solid surface where the flow cannot be predicted by continuum fluidics, and Navier-Stokes equations are used in the other regions. Numerical simulation of Couette flow was performed using the hybrid method to investigate the effect of solid-liquid interaction and surface roughness in a nanochannel. It was found that the solid-liquid interaction and surface roughness influence the boundary condition. When the surface energy is low, slippage occurs near the solid surface, and the magnitude of slippage decreases with increase in surface energy. When the surface energy is high, a locking boundary condition is formed. The roughness disturbs slippage near the solid surface and promotes the locking boundary condition.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1885-1890
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• 2013

In this paper, the electrical properties of nanoscale junctionless p-channel MuGFET at cryogenic temperature have been analyzed experimentally. The experiment was performed using a cryogenic probe station which uses the liquid Helium. It has been observed that the drain current oscillation at low drain voltage and cryogenic temperature was more pronounced in junctionless transistor than in accumulation mode transistor. The reason for more marked oscillation is due to the smaller electrical cross section area of the inversion channel which is formed at the center of silicon film in junctionless transistor. It was also observed that the drain current and maximum transconductance were increased as the measurement temperature increased. This is resulted from the increase of hole mobility and the decrease of the threshold voltage as the measurement temperature increases. The drain current oscillation due to the quantum effects can be occurred up to the room temperature when the device size scales down to the nanometer level.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.1-7
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• 2008

In this work, a two dimensional, self-consistent Poisson-$Schr{\ddot{o}}dinger$ solver has been implemented to study C-V characteristics in nanometer scale MuGFETs with considering quantum effects. The quantum-mechanical effects on gate-channel capacitance for different device dimension and gate configurations of nanometer scale MuGFETs have been analyzed. It has been found that 4he gate-channel capacitance per unit gate area is increased as the device dimension decreases. For different gate configurations, the gate-channel capacitance is decreased with increase of effective gate number. Those resu1ts have been explained by the distribution profile of electron concentration in the silicon surface and inversion capacitance. The length of inversion-layer centroid has been calculated from inversion capacitance with device dimension and gate configurations.