• Title/Summary/Keyword: 기생소자

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Experimental Study on the E-plane Coupled Rec tangular Microstrip Patch Antennas:Microstrip Line Fed Case (E-면 결합을 이용한 구형 마이크로스트립 안테나에 관한 실험적 연구 : 마이크로스트립 선로 급전)

  • Hong, Jae-Pyo;Cho, Young-Ki;Son, Hyon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.14 no.1
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    • pp.75-83
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    • 1989
  • In this paper, applying the REC model which characterizes the coupling between the radiating edges to two coupled rectangular microstrip patch antenna, we obtain scattering parameters $\mid$ $S_{11}$ $\mid$ and $\mid$ $S_{12}$ $\mid$for the various coupling separations, Se=0.5mm, 1.0mm, 1.5mm, and 2.0mm, The calculated values are compared with the measured values. For the rectangular microstrip patch antenna with a parasitic element which is gap-coupled to the radiating edges of the rectangular patch, calculated return losses using the REC model are compared with measrued values. Here, the each microstrip antenna is fed by a 50 microstrip line. The purpose of the paper is to compare a 50$\Omega$ microstrip line fed case with a coaxial fed case treated in Ref.

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Maximum Coupling Through a Narrow Slit in a Short-Ended Parallel-plate Waveguide with a Nearby Conducting Strip (단락종단된 평행평판 도파관의 좁은 슬릿을 통한 근접 도체스트립과의 최대 결합)

  • Lee, Jong-Ik;Jo, Yeong-Gi
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.37 no.12
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    • pp.15-21
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    • 2000
  • In this study, the electromagnetic coupling through a narrow slit in the upper wall of a short-ended parallel-plate waveguide(PPW) covered by a dielectric slab with a nearby conducting strip on the slab Is considered for the case that the TEM wave is incident in the PPW. Coupled integral equations whose unknowns are the slit electric field and the induced electric current over the strip are derived and solved numerically by use of the method of moments. From results, it has been observed that most of the incident power can be coupled exterior to the guide by appropriately setting the strip width and position, though the slit is very narrow. In addition, the differences between the radiation phenomena, observed in the cases that the conducting strip and the upper Plate of the PPW form a cavity and that strip behaves like a parasitic element, are discussed.

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ESD Failure Analysis of PMOS Transistors (PMOS 트랜지스터의 ESD 손상 분석)

  • Lee, Kyoung-Su;Jung, Go-Eun;Kwon, Kee-Won;Chun, Jung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.2
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    • pp.40-50
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    • 2010
  • The studies of PMOS transistors in CMOS technologies are reviewed- focusing on the snapback and breakdown behavior of the parasitic PNP BJTs in high current regime. A new failure mechanism of PMOSFET devices under ESD conditions is also analyzed by investigating various I/O structures in a $0.13\;{\mu}m$ CMOS technology. Localized turn-on of the parasitic PNP transistor can be caused by localized charge injection from the adjacent diodes into the body of the PMOSFET, significantly degrading the ESD robustness of PMOSFETs. Based on 2-D device simulations the critical layout parameters affecting this problem are identified. Design guidelines for avoiding this new PMOSFET failure mode are also suggested.

Study on the structure of buried type capacitor for MCM (Multi-Chip-Module) (MCM-C(Multi-Chip-Module)용 내장형 캐패시터의 구조적 특성에 관한 연구)

  • Yoo, C. S.;Lee, W. S.;Cho, H. M.;Lim, W.;Kwak, S. B.;Kang, N. K.;Park, J. C.
    • Journal of the Microelectronics and Packaging Society
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    • v.6 no.4
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    • pp.49-53
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    • 1999
  • In this study, the characteristics of the structure of buried type capacitor for RF multi- chip-module are investigated. We developed many kinds of structures to minimize the space of capacitor in module and the value of parastic series inductance without any loss in capacitance, and in this procedure the effect of vias especially position, size, number length are analyzed and optimized. This characteristics of structures are checked through HFSS(high frequency structure simulator) of HP, and the value of parastic series inductance is calculated by equivalent circuit analysis. And ensuing the result of simulation, we made buried type capacitors using LTCC (low temperature cofired ceramic) material. In measurement of this sample, we found out the effective and precise method can be applied to buried type and characteristics of vias and striplines added for measuring are quantified.

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OFDM Transmission Method Based on the Beam-Space MIMO System (빔공간 MIMO 시스템에 기반한 OFDM 전송방법)

  • Choi, Jinkyu;An, Changyoung;Ryu, Heung-Gyoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.40 no.3
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    • pp.425-431
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    • 2015
  • Beamspace Multiple-Input Multiple Output(MIMO) system can transmit multiple data by using Electronically Steerable Parasitic Array Radiator(ESPAR) antenna which has single Radio Frequency(RF)-chain. Beamspace MIMO system can reduce complexity of the system and size of antenna in comparison with the conventional MIMO system because of characteristic of ESPAR antenna using the single antenna and the RF-chain. Heretofore, only the research of transmitting single-carrier has been conducted by the use of beamspace MIMO system. Therefore, in this paper, we propose beamspace MIMO system based on Orthogonal Frequency Division Multiplexing(OFDM) for transmitting the multi-carrier and analysis the performance of this system. We find a proper reactance value which has good performance because proposed system changes the performance by the reactance values of parasitic elements. and we confirm that performance of the proposed system is similar to conventional MIMO system based on OFDM.

Design of RFID Mobile Antenna by Using Parasitic Element (기생 소자를 이용한 휴대 단말기용 RFID 리더 안테나)

  • Woo, Duk-Jae;Kim, Sung-Jin;Kim, Sang-Su;Kim, Yo-Sik;Lee, Kwang-Jae;Lee, Taek-Kyung
    • Journal of Advanced Navigation Technology
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    • v.11 no.1
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    • pp.72-78
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    • 2007
  • In this paper, the wide-band monopole antenna with a parasitic element on the ground plane for application in Cellular, GSM and RFID mobile terminals such as the mobile phone or Personal Digital Assistant(PDA) phone is presented. The VSWR of the designed antenna is 2:1 over the frequency range of 820 MHz to 1040 MHz(bandwidth of 23.6 %). Therefore, the designed antenna can provide wide bandwidth covering the Cellular(824 MHz~894 MHz), RFID(908.5 MHz~914 MHz) and GSM(Tx:880 MHz~915 MHz, Rx:925 MHz~960 MHz). The radiation characteristics of the fabricated antenna were also studied. According to the measured radiation patterns, the maximum gains at 859 MHz and 911.25 MHz(center frequencies of the Cellualr and RFID bands) are -0.7 dBi and 0.16 dBi, respectively. The measured maximum gains of GSM bands are -0.48 dBi(897.5 MHz, the center frequency of Tx) and 1.69 dBi(942.5 MHz, the center frequency of Rx).

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Breakdown Characteristics of Silicon Nanowire N-channel GAA MOSFET (실리콘 나노와이어 N-채널 GAA MOSFET의 항복특성)

  • Ryu, In Sang;Kim, Bo Mi;Lee, Ye Lin;Park, Jong Tae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.9
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    • pp.1771-1777
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    • 2016
  • In this thesis, the breakdown voltage characteristics of silicon nanowire N-channel GAA MOSFETs were analyzed through experiments and 3-dimensional device simulation. GAA MOSFETs with the gate length of 250nm, the gate dielectrics thickness of 6nm and the channel width ranged from 400nm to 3.2um were used. The breakdown voltage was decreased with increasing gate voltage but it was increased at high gate voltage. The decrease of breakdown voltage with increasing channel width is believed due to the increased current gain of parasitic transistor, which was resulted from the increased potential in channel center through floating body effects. When the positive charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was decreased due to the increased potential in channel center. When the negative charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was increased due to the decreased potential in channel center. We confirmed that the measurement results were agreed with the device simulation results.

Chaos QPSK Modulated Beamspace MIMO System Using ESPAR Antenna (ESPAR 안테나를 사용하는 카오스 QPSK 변조 빔 공간 MIMO 시스템)

  • Lee, Jun-Hyun;Bok, Jun-Yeong;Ryu, Heung-Gyoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39A no.2
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    • pp.77-85
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    • 2014
  • Recently, utilization of MIMO(Multi-Input Multi-Output) system using array antennas is evaluated significantly according to the extension of high-capacity and high-speed communication services. However, MIMO system has disadvantages such as high-complexity and high-power-consumption, because RF(Radio Frequency) chain is required as antenna number, and several array antenna is used in conventional MIMO system. In order to solve these problems, research about beamspace MIMO system using ESPAR(Electronically Steerable Parasitic Array Radiator) antenna that has single RF chain by using one active antenna and several parasitic elements has been studied actively. Beamspace MIMO system using ESPAR antenna is possible to solve the problems of conventional MIMO system, because this system is composed by single RF chain. In this paper, in order to improve the system security, chaos communication algorithm that has characteristics such as non-periodic, non-predictability, easy implementation and initial condition is applied to QPSK (Quadrature Phase Shift Keying) modulated beamspace MIMO system. We design the chaos QPSK modulated beamspace MIMO system, and evaluate SER performance of this system.

Stacked LTCC Band-Pass Filter for IEEE 802.11a (IEEE 802.11a용 적층형 LTCC 대역통과 여파기)

  • Lee Yun-Bok;Kim Ho-Yong;Lee Hong-Min
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.16 no.2 s.93
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    • pp.154-160
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    • 2005
  • Microwave Otters are essential device in modem wireless systems. A compact dimension BPF(Band-pass Filter) for IEEE 802.11a WLAN service is realized using LTCC multi-layer process. To extrude 2-stage band-pass equivalent circuit, band-pass and J-inverter transform applied to Chebyshev low-pass prototype filter. Because parallel L-C resonator is complicate and hard to control the inductor characteristics in high frequency, the shorted $\lambda/4$ stripline is selected for the resonator structure. The passive element is located in the different layers connected by conventional via structure and isolated by inner GND. The dimension of fabricated stacked band-pass filter which is composed of six layers, is $2.51\times2.27\times1.02\;mm^3$. The measured filter characteristics show the insertion loss of -2.25 dB, half-power bandwidth of 220 MHz, attenuation at 5.7 GHz of -32.25 dB and group delay of 0.9 ns at 5.25 GHz.

Bus Splitting Techniques for Low Power SoC Design (저 전력 시스템 온 칩 설계를 위한 버스 분할 기술)

  • Lim Hoyeong;Yoon Misun;Shin Hyunchul;Park Sungju
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.6
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    • pp.324-332
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    • 2005
  • In general, bus system consumes a very significant portion of power in a chip. Bus splitting can be used to reduce the energy dissipation and to reduce the Propagation delay on the bus by lowering the parasitic load of each bus segment. Data exchange probability distribution between a set of interconnected processing elements affects the average energy dissipation of the splitted bus architectures. In this research, we have developed tree-based bus splitting techniques and design methodologies, as an extension of horizontally aligned bus splitting. We have developed the methodology to select near-optimal bus architectures for low energy dissipation when data exchange probability distribution of a system is given. Experimental results show that the proposed techniques can reduce energy dissipation on the bus by up to 83$\%$.