• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.227-232
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• 2010

According to the development of ubiquitous and computer techniques, the application fields of sensor network have been enlarged. We present the design and implementation of sensor node which is the most important component of sensor network techniques in this paper. The proposed sensor node is implemented with 8-bit microprocessor, and temperature and humidity sensing device to gather temperature and humidity data in real world. It achieves low production cost and user convenience, and also has the feature os existing commercial sensor node. Though our experiments, we show that deviation of temperature and humidity are $5^{\circ}C$ and 23.2% respectively, and the proposed sensor node is reliable in real applications.

• Journal of Broadcast Engineering
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• v.15 no.3
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• pp.321-331
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• 2010

Most of multimedia video coding algorithms are lossy schemes and several kinds of spatial and temporal artifacts are inevitable. Flickering, which is the most typical coding artifact in time domain, is mainly due to fact that the quality of coded sequence fluctuates as the quantization parameter is adjusted for rate control. In this paper, we analyzed the effect of quality variation according to the characteristics of video sequence when the I-frames are periodically inserted. And we proposed the FR(Full Reference)-based assessment algorithm to measure the amount of flickering artifacts in the coded video. It is discovered that the flickering becomes critical when the level of quality is intermediate and is affected by the amount of detail or movement, the size of object, and camera parameters. The proposed measurement algorithm shows is well consistent with HVS(Human Visual System).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.12
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• pp.1834-1843
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• 2016

DVRs are the most common recording and displaying devices used for surveillance. Video compression plays a key role in DVRs for saving storage; the video compression standard, H.264/AVC, has recently become the dominant choice for DVRs. DVRs require various display modes, such as fast-forward, backward play, and pause; these are called trick modes. The implementation of precise trick mode play requires a very high decoding capability or a very intelligent scheme in order to handle the high computation complexity. The complexity is increased in many surveillance applications where more than one camera is used to monitor multiple spots or to monitor the same area using various angles. An implementation of a trick mode play and a frame buffer management scheme for the hardware-based H.264/AVC codec for multi-channel is presented in this paper. The experimental results show that exact trick mode play is possible using a standard H.264/AVC video codec with keyframe encoding feature at the expense of bitstream size increase.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.1
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• pp.36-40
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• 2003

A number of embedded wavelet image coding methods have been Proposed since the introduction of EZW(Embedded Zerotree Wavelet) algorithm. A common characteristic of these methods is that they use fundamental ideas found in the EZW algorithm. Especially, one of these methods is the SPIHT(Set Partitioning in Hierarchy Trees) algorithm, which became very popular since it was able to achieve equal or better performance than EZW without having to use an arithmetic encoder. The SPIHT algorithm is computationally very simple, but even so it provides excellent numerical and visual results. But the evaluation of its time complexity is no more than the relative result of experimental comparisons and the strict time complexity analysis wasn't taken until now. In this paper, we analyze strictly the processing time complexity of SPIHT algorithm and prove that the time complexity for one bit-plane processing is O( nlog $_2$n) in worst case.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.2
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• pp.47-54
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• 1990

In this paper, we design the 4-bit phase shifter which have $22.5^{\circ},45^{\circ},90^{\circ}$ and $180^{\circ}$ phase shift by applying the loaded line and switched network phase shifter. Its phase shift is variable with changing of the stub and passive device parameters. The experiments show the 6.5 dB average insertion loss and $10^{\circ}$ average phase error at center frequency, 6GHz. The results of experiment agree well with the theories except $180^{\circ}$ phase shifter.

• The Journal of Engineering Research
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• v.2 no.1
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• pp.31-37
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• 1997

This paper describes the design and implementation of 8 bit ALU graphic simulator which helps students who study the structure and operation course of general ALU. ALU of this paper consists of three parts, arithmetic circuit, logic circuit, and shifter. Each of them performs as follows. Arithmetic circuit performs arithmetic operation such as addition, subtraction, 1 increment, 1 decrement, 2's complement, logic circuit performs logic operation such as OR, AND, XOR, NOT, and shifter performs shift operation and transfers the result of circuits of arithmetic, logic to data bus. The instructions which relate to these basic ALU functions was selected from Z80 instructions and ALU circuit was designed with those instructions and this designed ALU circuit was implemented on graphic screen. And all state of this data operation course in ALU was showed by bit and logic gate unit.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.2
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• pp.41-51
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• 2004

In this paper, the beam steering dipole phased array antenna systems for IMT-2000 base station have been designed. The designed beam steering dipole phased array antenna systems are constituted by the antenna part and the beam steering control system part. The antenna part is designed by the proposed flat dipole for the broadband characteristics, and the 8${\times}$8 dipole array antenna is constructed by the proposed flat dipole for the directional radiation pattern. Besides the vertical power divider is designed for the vertical power distribution. The beam steering control system part is designed the horizontal power divider for the horizontal power distribution, the 4-bit phase shifters and the driving circuit of phase shifters for the horizontal beam tilting. In order to evaluate a performance of the designed antenna systems, they were fabricated and the radiation characteristics were measured. From the measured results, we found that the horizontal beams were tilted by the each control signals, and the measured radiation characteristics showed good agreement with the design goals.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.47-54
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• 2000

We designed asynchronous event logic library with 0.25um CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6GHz. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A Method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about $1.1mm{\times}1.1mm$.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.72-78
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• 2008

Although the H.264 video coding scheme is popular, it is not efficient for high-definition (HD) video coding because the size of its macroblock is relatively small for the HD video resolution. In this paper, we propose a new intra coding scheme based on the enlarged macroblock size. For the luminance component, intra $4{\times}4$ prediction and intra $16{\times}16$ prediction in H.264 are scaled into intra $8{\times}8$ prediction and intra $32{\times}32$ prediction, respectively. For the chrominance components, intra $8{\times}8$ prediction is extended to intra $16{\times}16$ prediction. Along with the $8{\times}8$ basic coding block size, an $8{\times}8$ integer discrete cosine transform (DCT) is used. Experimental results show that the proposed algorithm improves coding efficiency of the intra coding for HD video: PSNR gain by 0.23dB and bit-rate reduction by 5.32% on average.

• The KIPS Transactions:PartD
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• v.14D no.7
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• pp.801-808
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• 2007

Video coding standards such as MPEG-2, MPEG-4, H.263, and H.264 transmit a compressed video data using wired/wireless communication line with limited bandwidth. Because highly compressed bit-streams is likely to fragile to error from channel noise, video is damaged by error. There have been many research works on error concealment techniques, which recover transmission errors at decoder side [1, 2]. We designed an error concealment technique for lost motion vectors of H.264 video coding. In this paper, we propose a Kalman filter based motion vector recovery scheme, and experimented with standard video sequences. The experimental results show that our scheme restores original motion vector with more precision of 0.91 - 1.12 on average over conventional H.264 decoding with no error recovery.