• Title/Summary/Keyword: 기본비트

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Scrambling Technology using Scalable Encryption in SVC (SVC에서 스케일러블 암호화를 이용한 스크램블링 기술)

  • Kwon, Goo-Rak
    • Journal of Korea Multimedia Society
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    • v.13 no.4
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    • pp.575-581
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    • 2010
  • With widespread use of the Internet and improvements in streaming media and compression technology, digital music, video, and image can be distributed instantaneously across the Internet to end-users. However, most conventional Digital Right Management are often not secure and not fast enough to process the vast amount of data generated by the multimedia applications to meet the real-time constraints. The SVC offers temporal, spatial, and SNR scalability to varying network bandwidth and different application needs. Meanwhile, for many multimedia services, security is an important component to restrict unauthorized content access and distribution. This suggests the need for new cryptography system implementations that can operate at SVC. In this paper, we propose a new scrambling encryption for reserving the characteristic of scalability in MPEG4-SVC. In the base layer, the proposed algorithm is applied and performed the selective scambling. And it encrypts various MVS and intra-mode scrambling in the enhancement layer. In the decryption, it decrypts each encrypted layers by using another encrypted keys. Throughout the experimental results, the proposed algorithms have low complexity in encryption and the robustness of communication errors.

Performance Improvement of Binary MQ Arithmetic Coder (2진 MQ 산술부호기의 성능 개선)

  • Ko, Hyung Hwa;Seo, Seok Yong
    • Journal of Advanced Navigation Technology
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    • v.19 no.6
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    • pp.614-622
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    • 2015
  • Binary MQ arithmetic coding is widely used recently as a basic entropy coder in multimedia coding system. MQ coder esteems high in compression efficiency to be used in JBIG2 and JPEG2000. The importance of arithmetic coding is increasing after it is adopted as an unique entropy coder in HEVC standard. In the binary MQ coder, arithmetic approximation without multiplication is used in the process of recursive subdivision of range interval. Because of the MPS/LPS exchange activity happened in MQ coder, output byte tends to increase. This paper proposes an enhanced binary MQ arithmetic coder to make use of a lookup table for AQe using quantization skill in order to reduce the deficiency. Experimental results show that about 4% improvement of compression in case of JBIG2 for bi-level image compression standard. And also, about 1% improvement of compression ratio is obtained in case of lossless JPEG2000 coding. For the lossy JPEG2000 coding, about 1% improvement of PSNR at the same compression ratio. Additionally, computational complexity is not increasing.

Comparisons of Practical Performance for Constructing Compressed Suffix Arrays (압축된 써픽스 배열 구축의 실제적인 성능 비교)

  • Park, Chi-Seong;Kim, Min-Hwan;Lee, Suk-Hwan;Kwon, Ki-Ryong;Kim, Dong-Kyue
    • Journal of KIISE:Computer Systems and Theory
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    • v.34 no.5_6
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    • pp.169-175
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    • 2007
  • Suffix arrays, fundamental full-text index data structures, can be efficiently used where patterns are queried many times. Although many useful full-text index data structures have been proposed, their O(nlogn)-bit space consumption motivates researchers to develop more space-efficient ones. However, their space efficient versions such as the compressed suffix array and the FM-index have been developed; those can not reduce the practical working space because their constructions are based on the existing suffix array. Recently, two direct construction algorithms of compressed suffix arrays from the text without constructing the suffix array have been proposed. In this paper, we compare practical performance of these algorithms of compressed suffix arrays with that of various algorithms of suffix arrays by measuring the construction times, the peak memory usages during construction and the sizes of their final outputs.

The Characteristics of the Late Neoclassical Style in American Gardens - Focused on the analysis of Dumbarton Oaks by Beatrix Farrand - (미국 후기 신고전주의적 조경양식 특성 - 파란드의 덤바튼 오크(Dumbarton Oaks) 분석을 중심으로 -)

  • Lee, Hyung-Sook;Park, Eun-Yeong
    • Journal of the Korean Institute of Traditional Landscape Architecture
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    • v.32 no.2
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    • pp.159-166
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    • 2014
  • Beatrix Farrand was America's first female landscape architect and Dumbarton Oaks in Washington, D.C., USA site of her best known garden design. The purpose of this study is to identify characteristics of the American Neoclassical tendencies in the early 1900s and Farrand's style through an analysis of Dumbarton Oaks. The results of analysis indicated that although Dumbarton Oaks was influenced by many European classic gardens, the garden has the unique style which reflects regional contexts and culture based on the philosophy of arts and crafts movement, The major characteristics of the late Neoclassical style in America can be summarized as follows. First, A series of terraced gardens were connected by paths and stairways and natural terrain was preserved as much as possible. Second, the formal and informal style coexist and the symmetric and asymmetric forms are well-balanced throughout the garden. Third, selection of plant materials and planting methods, influenced by both classical gardens and the Arts and Crafts style in UK, are in harmony with the space configuration and shape.

Robust Blind- Video Watermarking against MPEG-4 Scalable Video Coding and Multimedia Transcoding (MPEG-4 스케일러블 비디오 코딩 및 멀티미디어 트랜스코딩에 강인한 블라인드 비디오 워터마킹)

  • Yoon, Ji-Sun;Lee, Suk-Hwan;Song, Yoon-Chul;Jang, Bong-Joo;Kwon, Ki-Ryong;Kim, Min-Hwan
    • Journal of Korea Multimedia Society
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    • v.11 no.10
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    • pp.1347-1358
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    • 2008
  • A blind video watermarking scheme for providing safety, authenticity, and copyright protection is proposed in this paper, which is robust to MPEG-4 SVC and multimedia transcoding. In proposed method, embedding and detecting of watermark is performed based on base layer with considering spatial SVC. To be robust from temporal SVC, our method embeds repeatedly a permutated character with ordering number per one frame. Also for robustness from multimedia transcoding and FGS, the method is embedded watermark in low middle frequency of each frame adaptively based on DCT in ROI. Through experimental results, invisibility of the watermark is confirmed and robustness of the watermark against the spatial SVC, temporal SVC, FGS and video transcoding between MPEG-2 and MPEG-4 SVC is also verified.

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Studies on Joint Source/Channel Coding for MPEG-4 Scalable Video Transmission in Mobile Broadcast Receiving Environments (이동방송수신환경에서 MPEG-4 계층적 비디오 전송을 위한 결합 소스/채널 부호화에 관한 연구)

  • Lee Woon-Moon;Sohn Won
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.42 no.3 s.303
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    • pp.31-40
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    • 2005
  • In this paper, we develop an approach toward JSC(Joint Source-Channel Coding) method for MPEG-4 based FGS(Fine Granular Scalability) video coding and transmission in fixed and mobile receiving environment(Digital Audio Broadcasting, DAB). The source coder used MPEG-4 FGS video codec, the channel coder used RCPC(Rate Compatible Punctured Convolution) code and the modulation method used QPSK modulation. We have considered channel environment of AWGN and mobile receiving environment. This study determined optimum Trade-off point between source bit rate and channel coding rate in variable channel states. We compared FGS-JSC method and general single layer CBR(Constant Bit Rate) transmission. In this results, FGS-JSC was appeared better performance than CBR transmission.

Area-Efficient Semi-Parallel Encoding Structure for Long Polar Codes (긴 극 부호를 위한 저 면적 부분 병렬 극 부호 부호기 설계)

  • Shin, Yerin;Choi, Soyeon;Yoo, Hoyoung
    • Journal of IKEEE
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    • v.23 no.4
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    • pp.1288-1294
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    • 2019
  • The channel-achieving property made the polar code show to advantage as an error-correcting code. However, sufficient error-correction performance shows the asymptotic property that is achieved when the length of the code is long. Therefore, efficient architecture is needed to realize the implementation of very-large-scale integration for the case of long input data. Although the most basic fully parallel encoder is intuitive and easy to implement, it is not suitable for long polar codes because of the high hardware complexity. Complementing this, a partially parallel encoder was proposed which has an excellent result in terms of hardware area. Nevertheless, this method has not been completely generalized and has the disadvantage that different architectures appear depending on the hardware designer. In this paper, we propose a hardware design scheme that applies the proposed systematic approach which is optimized for bit-dimension permutations. By applying this solution, it is possible to design a generalized partially parallel encoder for long polar codes with the same intuitive architecture as a fully parallel encoder.

VLSI Design of a 2048 Point FFT/IFFT by Sequential Data Processing for Digital Audio Broadcasting System (순차적 데이터 처리방식을 이용한 디지틀 오디오 방송용 2048 Point FFT/IFFT의 VLSI 설계)

  • Choe, Jun-Rim
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.5
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    • pp.65-73
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    • 2002
  • In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

Development of Control Board for Coding Education and Convergence Contents based on 3D Printing (코딩 교육용 제어 보드와 3D 프린팅 융복합 콘텐츠 개발)

  • Youm, Sung-Kwan;Kim, Young-Sang
    • Journal of the Korea Convergence Society
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    • v.9 no.9
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    • pp.1-8
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    • 2018
  • It is a key role in leading and activating coding education as a process to solve problems creatively to produce and provide the educational contents on the basis of 3D printing. In this paper, we develop a variety of fusion contents to use 3D printing and 8bit MCU base control board which provides specific functions through Arduino. The developed control program conducts various packet monitoring more than ten times per a second, supporting intrinsically full duplex. In addition, communication protocol optimized in conveying a lot of information enables to control different contents. The contents produced with the control board and 3D printing are useful as a programming education tool to train the principle and the concept of coding.

An Efficient Bit Stream Instruction-set for Network Packet Processing Applications (네트워크 패킷 처리를 위한 효율적인 비트 스트림 명령어 세트)

  • Yoon, Yeo-Phil;Lee, Yong-Surk;Lee, Jung-Hee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.10
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    • pp.53-58
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    • 2008
  • This paper proposes a new set of instructions to improve the packet processing capacity of a network processor. The proposed set of instructions is able to achieve more efficient packet processing by accelerating integration of packet headers. Furthermore, a hardware configuration dedicated to processing overlay instructions was designed to reduce additional hardware cost. For this purpose, the basic architecture for the network processor was designed using LISA and the overlay block was optimized based on the barrel shifter. The block was synthesized to compare the area and the operation delay, and allocated to a C-level macro function using the compiler known function (CKF). The improvement in performance was confirmed by comparing the execution cycle and the execution time of an application program. Experiments were conducted using the processor designer and the compiler designer from Coware. The result of synthesis with the TSMC ($0.25{\mu}m$) from Synopsys indicated a reduction in operation delay by 20.7% and an improvement in performance of 30.8% with the proposed set of instructions for the entire execution cycle.