• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.10
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• pp.827-832
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• 2013

Holographic data storage system is affected by two dimensional intersymbol interference and inter-page interference. Especially, for multi-level holographic data storage system, since one pixel contains more than 1 bit, the system is more vulnerable to the error. In this paper, we propose a 2/3 modulation code for 4-level holographic data storage system. The proposed modulation code with error correcting capability could be compensated these interferences. Also, in this paper, we proposed a Viterbi decoder for 2/3 modulation code. The proposed Viterbi decoder eliminates unnecessary calculation. As a result, proposed 2/3 modulation code and Viterbi decoder has shown better performance than conventional one.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.190-196
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• 2013

Curved integral imaging is a simple method to display 3D images in space using lens array and provides wide viewing angle. In this paper, we propose a nonlinear 3D correlator based on the direct pixel-mapping (DPM) method in order to improve the recognition performance of 3D target object in curving-effective integral imaging. With this scheme, the elemental image array (EIA) originally picked up from a partially occluded 3-D target object can be converted into a resolution enhanced new EIA by using DPM method. Then, through nonlinear cross-correlations between the reconstructed reference and the target plane images, the improved pattern recognition can be performed from the correlation outputs. To show the feasibility of the proposed method, some preliminary experiments are carried out and results are presented by comparing the conventional method.

• KIPS Transactions on Software and Data Engineering
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• v.2 no.4
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• pp.273-280
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• 2013

This paper presents novel OCS-LBP (Oriented Center Symmetric Local Binary Patterns) based on orientation of pixel gradient and image retrieval system based on BoF (Bag-of-Feature) and random forest classifier. Feature vectors extracted from training data are clustered into code book and each feature is transformed new BoF feature using code book. BoF features are applied to random forest for training and random forest having N classes is constructed by combining several decision trees. For testing, the same OCS-LBP feature is extracted from a query image and BoF is applied to trained random forest classifier. In contrast to conventional retrieval system, query image selects similar K-nearest neighbor (K-NN) classes after random forest is performed. Then, Top K similar images are retrieved from database images that are only labeled K-NN classes. Compared with other retrieval algorithms, the proposed method shows both fast processing time and improved retrieval performance.

• Journal of Bio-Environment Control
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• v.24 no.3
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• pp.210-216
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• 2015

Purpose of this study was a development of an image processing algorithm to recognize paprika and acquire it's 3D coordinates from stereo images to precisely control an end-effector of a paprika auto harvester. First, H and S threshold was set using HSI histogram analyze for extracting ROI(region of interest) from raw paprika cultivation images. Next, fundamental matrix of a stereo camera system was calculated to process matching between extracted ROI of corresponding images. Epipolar lines were acquired using F matrix, and $11{\times}11$ mask was used to compare pixels on the line. Distance between extracted corresponding points were calibrated using 3D coordinates of a calibration board. Non linear regression analyze was used to prove relation between each pixel disparity of corresponding points and depth(Z). Finally, the program could calculate horizontal(X), vertical(Y) directional coordinates using stereo camera's geometry. Horizontal directional coordinate's average error was 5.3mm, vertical was 18.8mm, depth was 5.4mm. Most of the error was occurred at 400~450mm of depth and distorted regions of image.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.101-109
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• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.875-878
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• 2015

In this paper, we propose an intra prediction hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC encoder. The proposed intra prediction hardware architecture uses common operation units to reduce computational complexity and uses $4{\times}4$ block unit to reduce hardware area. In order to reduce operation time, common operation unit uses one operation unit to generate predicted pixels and filtered pixels in all prediction modes. Intra prediction hardware architecture introduces the $4{\times}4$ PU design processing to reduce the hardware area and uses intemal registers to support $32{\times}32$ PU processmg. The proposed hardware architecture uses ten common operation units which can reduce execution cycles of intra prediction. The proposed Intra prediction hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 41.5k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 150MHz, it can support 4K UHD video encoding at 30fps in real time, and operates at a maximum of 200MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1203-1212
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• 2013

In this paper, an intra prediction hardware architecture is proposed to reduce computational complexity of intra prediction in HEVC decoder. The architecture uses shared operation units and common operation units and adopts a fast smoothing decision algorithm and a fast algorithm to generate coefficients of a filter. The shared operation unit shares adders processing common equations to remove the computational redundancy. The unit computes an average value in DC mode for reducing the number of execution cycles in DC mode. In order to reduce operation units, the common operation unit uses one operation unit generating predicted pixels and filtered pixels in all prediction modes. In order to reduce processing time and operators, the decision algorithm uses only bit-comparators and the fast algorithm uses LUT instead of multiplication operators. The proposed architecture using four shared operation units and eight common operation units which can reduce execution cycles of intra prediction. The architecture is synthesized using TSMC 0.13um CMOS technology. The gate count and the maximum operating frequency are 40.5k and 164MHz, respectively. As the result of measuring the performance of the proposed architecture using the extracted data from HM 7.1, the execution cycle of the architecture is about 93.7% less than the previous design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.8C
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• pp.505-515
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• 2011

This paper describes a normalization method of Haar-like features used for object detection. Previous method which performs variance normalization on Haar-like features requires a lot of calculations, since it uses an additional integral image for calculating the standard deviation of intensities of pixels in a candidate window and increases possibility of false detection in the area where variance of brightness is small. The proposed normalization method can be performed much faster than the previous method by not using additional integral image and classifiers which are trained with the proposed normalization method show robust performance in various lighting conditions. Experimental result shows that the object detector which uses the proposed method is 26% faster than the one which uses the previous method. Detection rate is also improved by 5% without increasing false alarm rate and 45% for the samples whose brightness varies significantly.

• Journal of Broadcast Engineering
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• v.4 no.2
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• pp.144-154
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• 1999

The binomial sequences are family of orthogonal sequences that can be generated with remarkable simplicity-no multiplications are necessary. This paper introduces a class of non-recursive multidimensional filters for frequency-selective image processing without multiplication operations. The magnitude responses are narrow-band. approximately gaussian-shaped with center frequencies which can be positioned to yield low-pass. band-pass. or high-pass filtering. Algorithms for the efficient implementation of these filters in software or in hardware are described. Also. we show that the binomial QMFs are the maximally flat magnitude square Perfect Reconstruction paraunitary filters with good compression capability and these are shown to be wavelet filters as well. In wavelet transform the original image is decomposed at different scales using a pyramidal algorithm architecture. The decomposition is along the vertical and horizontal direction and maintains constant the number of pixels required to describe the images. An efficient perfect reconstruction binomial QMF-Wavelet signal decomposition structure is proposed. The technique provides a set of filter solutions with very good amplitude responses and band split. The proposed binomial QMF-filter structure is efficient, simple to implement on VLSl. and suitable for multi-resolution signal decomposition and coding applications.

• The KIPS Transactions:PartB
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• v.15B no.6
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• pp.543-552
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• 2008

ATIS(Advanced Traveler Information System) is the system to offer a real-time traffic information or traffic situation for the benefit of the client. One of traffic information collection methods for ATIS research is the method of image analysis. The method is divided into two : one is the method to set two loop detectors at the area and the other is the method detecting the vehicle through an image analysis. In this paper, we propose a real-time traffic information collection system to mix two methods. The system installs multiple virtual detection lines and traces the location of the vehicle. Use of multiple virtual detection lines supplements the defect of the method of loop detectors. And we drew a representative pixels in the detecting area and used it for image analysis. This is to solve the problem of time delay which increases as the image size increases. We gathered traffic images and experimented using the system and got 92.32% of detection accuracy.