• The KIPS Transactions:PartC
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• v.10C no.7
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• pp.937-942
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• 2003

In this paper, we measured and examined RTT delays and packet losses according to the changes of stationary loads for two typical stream-type traffics, a DV and a MPGE2 on the R＆D Gigabit Network testbed, JGN. As the result of our actual measurements, we realized that the packet size of stationary load have no effects on a DV and a MPGE2 stream on the very high-speed network(50Mbps, IP over ATM). When its bandwidth and stationary load exceeds 95％ of network bandwidth, packet losses appeared and RTT delay increased rapidly. Also we realized that the number and size of Receive ＆ Transmit buffer on the end systems have no effects on packet losses and RTT delays.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.4
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• pp.369-377
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• 2008

Today, Ethernet technology is rapidly developing to have a bandwidth of 10Gbps beyond 1Gbps. In such high-speed networks, the existing method that host CPU processes TCP/IP in the operating system causes numerous overheads. As a result of the overheads, user applications cannot get the enough computing power from the host CPU. To solve this problem, the TCP/IP Offload Engine(TOE) technology was emerged. TOE is a specialized NIC which processes the TCP/IP instead of the host CPU. In this paper, we implemented a high-performance, lightweight TCP/IP(HL-TCP) for the TOE and applied it to an embedded system. The HL-TCP supports existing fundamental TCP/IP functions; flow control, congestion control, retransmission, delayed ACK, processing out-of-order packets. And it was implemented to utilize Ethernet MAC's hardware features such as TCP segmentation offload(TSO), checksum offload(CSO) and interrupt coalescing. Also we eliminated the copy overhead from the host memory to the NIC memory when sending data and we implemented an efficient DMA mechanism for the TCP retransmission. The TOE using the HL-TCP has the CPU utilization of less than 6% and the bandwidth of 453Mbps.

• Journal of the Korea Society of Computer and Information
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• v.10 no.6 s.38
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• pp.209-218
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• 2005

In this paper, we present an Active Optical Network(AON) . The AON uses the Dense Wavelength Division Multiplexing(DWDM) from optical communication access network of ring type, and will be able to provide the smoothly service in the Bandwidth on Demand by using DWDM. It supports the connection of the multiple wavelength and the Sub-Carrier from the optical gigabit ethernet switch. The Wavelength Add Drop Multiplexer(WADM) extracts a specific wavelength, and composes a node of the ring network. The specific wavelength becomes demultiplexing in the Sub-Carrier and it is distributed in the user The active connection of optical gigabit ethernet switch where the distribution of access network is started and access terminal connection equipment is possible. By the BoD from the AON it compares the buffer size which changes, and it analyzes. Also the Time delay of bit compares with the throughput of server The limit of amount of time is decided. Consequently it will be able to realize the dynamic use protocol and an efficient algorithm of the network.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.104-113
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• 2013

A high-throughput Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture is proposed for 60GHz multi-gigabit wireless personal area network (WPAN) applications. Two novel techniques which can apply to our selected QC-LDPC code are proposed, including a four block-parallel layered decoding technique and fixed wire network. Two-stage pipelining and four block-parallel layered decoding techniques are used to improve the clock speed and decoding throughput. Also, the fixed wire network is proposed to simplify the switch network. A 672-bit, rate-1/2 QC-LDPC decoder architecture has been designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed QC-LDPC decoder requires a 794K gate and can operate at 290 MHz to achieve a data throughput of 3.9 Gbps with a maximum of 12 iterations, which meet the requirement of 60 GHz WPAN applications.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.7 s.349
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• pp.93-103
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• 2006

Network solutions for protecting against worm attacks that complement partial end system patch deployment is a pressing problem. In the content-based worm filtering, the challenges focus on the detection accuracy and its performance enhancement problem. We present a worm filter architecture using the bloom filter for deployment at high-speed transit points on the Internet, including firewalls and gateways. Content-based packet filtering at multi-gigabit line rates, in general, is a challenging problem due to the signature explosion problem that curtails performance. We show that for worm malware, in particular, buffer overflow worms which comprise a large segment of recent outbreaks, scalable -- accurate, cut-through, and extensible -- filtering performance is feasible. We demonstrate the efficacy of the design by implementing it on an Intel IXP network processor platform with gigabit interfaces. We benchmark the worm filter network appliance on a suite of current/past worms, showing multi-gigabit line speed filtering prowess with minimal footprint on end-to-end network performance.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.319-321
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• 2005

한국천문연구원에서는 한국우주전파관측망(Korean VLBI Network; KVN)에서 사용할 관측 시스템 중에서 소규모 자료획득시스템(DAS) 구축을 위하여 기가비트 고속샘플러, PC-VSI 보드, 소프트웨어 상관기를 도입하였다. 고속샘플러는 기가비트급 ADS1000, PC-VSI 보드는 VSI-H(VLBI Standard Interface Hardware) 표준을 따른 PCI 버스를 채택하고 있어 일반 컴퓨터에 설치하여 동작되며, 이 규격을 갖춘 시스템과의 데이터 입출력이 가능하다. 소프트웨어 상관기는 일본 NILT와의 연구협력을 통하여 본 연구원에서도 사용할 수 있게 되었으며, FX와 XF 형 2가지를 모두 갖추고 있다. 하지만 현재 구현된 소프트웨어 상관기는 측지 VLBI 관측을 위해 설계되어 있어, 향후 KVN의 하드웨어 상관기와 함께 천문 VLBI 관측을 위한 3기선 분의 소프트웨어 상관기로 개량하려고 한다. 이상에서 소개한 시스템을 좁은 의미로 K5 시스템이라고도 한다. 본 논문에서는 PC-VSI 보드에 대해 간략히 소개하고, K5 시스템을 이용하여 관측한 결과를 빨리 관측자가 원하는 정보를 얻을 수 있는 소프트웨어 상관기의 구조에 대해서도 소개하고자 한다.

• Journal of KIISE:Information Networking
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• v.30 no.2
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• pp.282-292
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• 2003

This paper proposes an efficient data structure for forwarding IPv4 and IPv6 packets at the gigabit speed in backbone routers. The LPM(Longest Prefix Matching) search becomes a bottleneck of routers' performance since the LPM complexity grows in proportion to the forwarding table size and the address length. To speed up the forwarding process, this paper introduces a data structure named BMT(Bit-Map Tie) to minimize the frequent main memory accesses. All the necessary search computations in BMT are done over a small index table stored at cache. To build the small index table from the tie representation of the forwarding table, BMT represents a link pointer to the child node and a node pointer to the corresponding entry in the forwarding table with one bit respectively. To improve the poor performance of the conventional tries when their height becomes higher due to the increase of the address length, BMT adopts a binary search algorithm for determining the appropriate level of tries to start. The simulation experiments show that BMT compacts the IPv4 backbone routers' forwarding table into a small one less than 512-kbyte and achieves the average speed of 250ns/packet on Pentium II processors, which is almost the same performance as the fastest conventional lookup algorithms.

• The Magazine of the IEIE
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• v.29 no.10
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• pp.1175-1175
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• 2002

2002년 6월, IEEE 802.3ae 10Gb/s 이더넷이 표준으로 승인되었다. 10 Gb/s 이더넷은 MAC 부계층과 물리계층을 통합한 규격으로 전이중 방식 및 광섬유 매체만을 제공한다. 기존 이더넷과 동일한 프레임 형식을 사용하고, LAN 물리계층과 WAN 물리계층까지 지원하고 있다. 따라서 LAN, MAN, WAN 영역에서 10Gb/s의 높은 속도를 제공할 수 있으며, 기존의 이더넷과 투명하게 통합할 수 있다. 본 논문에서는 10 기가비트 이더넷의 MAC 부계층과 물리계층 및 최근 기술 동향을 살펴본다.

• The Magazine of the IEIE
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• v.29 no.10
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• pp.29-38
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• 2002

2002년 6월, IEEE 802.3ae 10Gb/s 이더넷이 표준으로 승인되었다. 10 Gb/s 이더넷은 MAC 부계층과 물리계층을 통합한 규격으로 전이중 방식 및 광섬유 매체만을 제공한다.기존 이더넷과 동일한 프레임 형식을 사용하고, LAN 물리계층과 WAN 물리계층까지 지원하고 있다. 따라서 LAN, MAN, WAN 영역에서 10Gb/s의 높은 속도를 제공할 수 있으며, 기존의 이더넷과 투명하게 통합할 수 있다. 본 논문에서는 10 기가비트 이더넷의 MAC 부계층과 물리계층 및 최근 기술 동향을 살펴본다.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.149-153
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• 1999

As VLSI technology advances rapidly, the operating frequency of digital systems becomes very fast. In such a high-speed system, there are many factors that threaten signal integrity. The noise sources in digital system include the noises in power supply, ground bounce and packaging media and distortions on single and multiple transmission lines. This paper will present a technology survey useful in the design of Gigabit interconnection systems. Some case studies have been constructed which show the lossy transmission line effect of skin effect. dielectric loss, with backplane connectors using the theoretical and practical conditions.