• Title/Summary/Keyword: 금속-실리콘 네트워크

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Heat Conduction Analysis of Metal Hybrid Die Adhesive Structure for High Power LED Package (고출력 LED 패키지의 열 전달 개선을 위한 금속-실리콘 병렬 접합 구조의 특성 분석)

  • Yim, Hae-Dong;Choi, Bong-Man;Lee, Dong-Jin;Lee, Seung-Gol;Park, Se-Geun;O, Beom-Hoan
    • Korean Journal of Optics and Photonics
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    • v.24 no.6
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    • pp.342-346
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    • 2013
  • We present the thermal analysis result of die bonding for a high power LED package using a metal hybrid silicone adhesive structure. The simulation structure consists of an LED chip, silicone die adhesive, package substrate, silicone-phosphor encapsulation, Al PCB and a heat-sink. As a result, we demonstrate that the heat generated from the chip is easily dissipated through the metal structure. The thermal resistance of the metal hybrid structure was 1.662 K/W. And the thermal resistance of the total package was 5.91 K/W. This result is comparable to the thermal resistance of a eutectic bonded LED package.

Topology Design for Energy/Latency Optimized Application-specific Hybrid Optical Network-on-Chip (HONoC) (특정 용도 하이브리드 광학 네트워크-온-칩에서의 에너지/응답시간 최적화를 위한 토폴로지 설계 기법)

  • Cui, Di;Lee, Jae Hoon;Kim, Hyun Joong;Han, Tae Hee
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.11
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    • pp.83-93
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    • 2014
  • It is a widespread concern that electrical interconnection based network-on-chip (NoC) will ultimately face the limitation in communication bandwidth, transmission latency and power consumption in the near future. With the development of silicon photonics technology, a hybrid optical network-on-chip (HONoC) which embraces both electrical- and optical interconnect, is emerging as a promising solution to overcome these problems. Today's leading edge systems-on-chips (SoCs) comprise heterogeneous many-cores for higher energy efficiency, therefore, extended study beyond regular topology based NoC is required. This paper proposes an energy and latency optimization topology design technique for HONoC taking into account the traffic characteristics of target applications. The proposed technique is implemented with genetic algorithm and simulation results show the reduction by 13.84% in power loss and 28.14% in average latency, respectively.