• Title/Summary/Keyword: 근사슬

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Head Slider Design Using Approximation Method For Load/Unload Applications (근사화 기법을 이용한 Load/Unload 용 헤드 슬라이더 최적설계)

  • Son, Seok-Ho;Yoon, Sang-Joon;Park, No-Cheol;Park, Young-Pil;Choi, Dong-Hoon
    • Transactions of the Society of Information Storage Systems
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    • v.2 no.3
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    • pp.169-177
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    • 2006
  • In this study, we present the optimization of a head slider using kriging method in order to reduce lift-off force during unloading process with satisfying reliable flying attitude in steady state. To perform an optimization process efficiently, a simplified lift-off force model, which is a function of air bearing suction force and flying attitudes, is created by kriging method. The EMDIOS, which is the process integration and design optimization software developed by iDOT, is used to automatically wrap the analysis with the optimization and efficiently implements the repetitive works between analyzer and optimizer. An optimization problem is formulated to reduce the lift-off force during unloading process while satisfying the flying attitude in reliable range over the entire recording band and reducing the probability of contact between slider and disk. The simulation result shows that the amplitude of lift-off force of optimized L/UL slider is reduced about 62%, compared with that of initial slider model. It is demonstrated by the dynamics L/UL simulation that the optimum slider incorporated with the suspension is not only smoothly loaded onto disk but also properly unloaded onto the ramp.

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Effect of Dynamic Tubing Gait Training for Life-Care on Balance of Stroke Patients (라이프케어 증진을 위한 동적탄력튜빙 보행훈련이 뇌졸중 환자의 균형에 미치는 영향)

  • Lee, Seon-Yeong;Lee, Dong-Ryul
    • Journal of Korea Entertainment Industry Association
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    • v.15 no.1
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    • pp.171-180
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    • 2021
  • The present study investigated the effects of dynamic tubing gait (DTG II) program on the balancing ability for the promotion of life care of patients with chronic stroke. In the study, 25 sessions of DTG II program (30 minutes per session, 5 sessions per week, for a total of 5 weeks) were applied to 10 patients with chronic stroke. To determine the effects of DTG II program for improving balance, surface electromyography(external oblique, erector spinae, iliopsoas, gluteus maximus), symmetry index test on three pelvic axes, and dynamic gait index test were performed before and after the intervention. The results showed statistically significant differences between preand post-intervention measurements of the gluteus maximus muscle at early and mid-stance phases(p<.05). The pelvic symmetry index differed significantly between pre- and post-intervention measurements of diagonal and rotational movement(p<.05). Comparison of dynamic gait index also showed statistically significant differences between pre- and post-intervention measurements(p<.05). Based on these findings, it was determined that the DTG II program was able to improve the balancing ability of patients with chronic stroke by activating their trunk muscles and improving the symmetry of diagonal pelvic movement and rotation. Therefore, DTG II program is recommended as an interventional method to improve life-care through improving the balancing ability of patients with chronic stroke.

A Simple Transcoding Method for H.264 Coding System (H.264 부호화시스템에서 간단한 비트열 변환 기법)

  • Yang, Young-Hyun;Kwon, Soon-Kak
    • Journal of Korea Multimedia Society
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    • v.9 no.7
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    • pp.818-826
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    • 2006
  • In this paper, we investigate the relationship of bitrate and quantization parameter needed for the trans-coding method that makes the H.264 bitstream of a particular bitrate to the other titrate. Also we propose the new method in order to transcode the titrate between H.264 video coded bitstreams. The proposed transcoding method updates the model parameters from previous picture or slice by using the approximated relationship of bitrate and quantization step-size and finds the target quantization step-size, and then generates the target titrate by simple coding processing just after requantization. Therefore, the proposed method does not need the complex bitrate control and converts to the target titrate by simple implementation. From simulation, we can see that the proposed method transcodes exactly to an assigned target bitrate for the four test sequences with different their characteristics.

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A Hardware Implementation of EGML-based Moving Object Detection Algorithm (EGML 기반 이동 객체 검출 알고리듬의 하드웨어 구현)

  • Kim, Gyeong-hun;An, Hyo-sik;Shin, Kyung-wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.10
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    • pp.2380-2388
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    • 2015
  • A hardware implementation of MOD(moving object detection) algorithm using EGML(effective Gaussian mixture learning)- based background subtraction to detect moving objects in video is described. Some approximations of EGML calculations are applied to reduce hardware complexity, and pipelining technique is adopted to improve operating speed. The MOD processor designed in Verilog-HDL has been verified by FPGA-in-the-loop verification using MATLAB/Simulink. The MOD processor has 2,218 slices on the Virtex5-XC5VSX95T FPGA device and its throughput is 102 MSamples/s at 102 MHz clock frequency. Evaluation results of the MOD processor for 12 images in the IEEE CDW-2012 dataset show that the average recall value is 0.7631, the average precision value is 0.7778 and the average F-measure value is 0.7535.

A Small-area Hardware Implementation of EGML-based Moving Object Detection Processor (EGML 기반 이동객체 검출 프로세서의 저면적 하드웨어 구현)

  • Sung, Mi-ji;Shin, Kyung-wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.12
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    • pp.2213-2220
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    • 2017
  • This paper proposes an efficient approach for hardware implementation of moving object detection (MOD) processor using effective Gaussian mixture learning (EGML)-based background subtraction method. Arithmetic units used in background generation were implemented using LUT-based approximation to reduce hardware complexity. Hardware resources used for both background subtraction and Gaussian probability density calculation were shared. The MOD processor was verified by FPGA-in-the-loop simulation using MATLAB/Simulink. The MOD performance was evaluated by using six types of video defined in IEEE CDW-2014 dataset, which resulted the average of recall value of 0.7700, the average of precision value of 0.7170, and the average of F-measure value of 0.7293. The MOD processor was implemented with 882 slices and block RAM of $146{\times}36kbits$ on Virtex5 FPGA, resulting in 60% hardware reduction compared to conventional design based on EGML. It was estimated that the MOD processor could operate with 75 MHz clock, resulting in real-time processing of $800{\times}600$ video with a frame rate of 39 fps.