• Journal of the Korea Convergence Society
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• v.12 no.12
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• pp.273-280
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• 2021

This paper presents the results of study of linear oscillating electric machine; Cartesian, cylindrical type with permanent magnet, flux reversal, cylindrical reluctance, and transverse flux type. The focus of the work is the suggestion of the characteristics and design process of propose topology, respectively. First of all, there are five types of the proposed to this study on the basis of the existing literatures; Cartesian type, cylindrical type, flux reversal type, cylindrical reluctance type, and transverse flux type. All topology is achieved using equivalent magnetic circuit considering leakage elements as initial modeling. Cartesian type is investigated by number of phases and number of pole pairs using optimal process. A cylindrical type is described by number of phases and displacement of stroke. The flux reversal type is proposed based on the symmetrical and non symmetrical stator cores of the surface mounted PMs mover, and non slanted PMs and slanted PMs of the flux concentrating PMs mover. A cylindrical reluctance type is studied by the shape of mover teeth in geometric aspect to reduce force ripple and increase magnetic flux. A transverse flux type is considered by dividing the transverse flux electric excited and the transverse flux permanent magnet excited. It is significant that the study gives a design rules and features of linear oscillating electric machine.

• Journal of IKEEE
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• v.25 no.4
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• pp.625-633
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• 2021

This paper describes a scalable architecture for flexible hardware implementation of Montgomery modular multiplication. Our scalable modular multiplier architecture, which is based on a one-dimensional array of processing elements (PEs), performs word parallel operation and allows us to adjust computational performance and hardware complexity depending on the number of PEs used, N_PE. Based on the proposed architecture, we designed a scalable Montgomery modular multiplier (sMM) core supporting eight field sizes defined in SEC2. Synthesized with 180-nm CMOS cell library, our sMM core was implemented with 38,317 gate equivalents (GEs) and 139,390 GEs for N_PE=1 and N_PE=8, respectively. When operating with a 100 MHz clock, it was evaluated that 256-bit modular multiplications of 0.57 million times/sec for N_PE=1 and 3.5 million times/sec for N_PE=8 can be computed. Our sMM core has the advantage of enabling an optimized implementation by determining the number of PEs to be used in consideration of computational performance and hardware resources required in application fields, and it can be used as an IP (intellectual property) in scalable hardware design of elliptic curve cryptography (ECC).

• Journal of Life Science
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• v.33 no.6
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• pp.490-497
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• 2023

Pregnant women may need to take medications to treat preexisting diseases or diseases that develop during pregnancy. However, some drugs may be fetotoxic and lead to, for example, teratogenicity and growth retardation. Predicting the fetotoxicity of drugs is thus important for the health of the mother and fetus. The fetotoxicity of many drugs has not been established because various challenges hinder the ability of researchers to determine their fetotoxicity. The need exists for in silico-based fetotoxicity assessment models, as they can modernize the testing paradigm, improve predictability, and reduce the use of animals and the costs of fetotoxicity testing. In this study, we collected data on the fetotoxicity of drugs and constructed fetotoxicity prediction models based on various machine learning algorithms. We optimized the models for more precise predictions by tuning the hyperparameters. We then performed quantitative performance evaluations. The results indicated that the constructed machine learning-based models had high performance (AUROC >0.85, AUPR >0.9) in fetotoxicity prediction. We also analyzed the feature importance of our model's predictions, which could be leveraged to identify the specific features of drugs that are strongly associated with fetotoxicity. The proposed model can be used to prescreen drugs and drug candidates at a lower cost and in less time. It provides a predictive score for fetotoxicity risk, which may be beneficial in the design of studies on fetotoxicity in human pregnancy.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2004.11a
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• pp.159-166
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• 2004

The beach, a margin between the sea and the land, is an extremely dynamic zone, for it is here that the motion of the sea interacts with the sediment, rock of the land or the artificial barriers. In order to prohibit or retard erosions due to the extreme Typhoon or storm induced waves, man has constructed these of temporary or more permanent nature, but they caused problems of other erosions from the secondary effect of them and a bad influence on the seascape. In considering the energy available to accelerate sediment transport and erosion in the surf zone, where the waves are broken, and offshore beyond the breaker line, the wave height and the wave period should be taken account. Hence, we tried to present an applicability of the submerged artificial Bio-reefs analyzing waves by a numerical model such that they could reduce the wave power without the secondary effect and restoration of marine ecologies. A new technique of beach preservation is by artificial reefs with artificial and/or natural kelps or sea plants. By engineering the geometry of the nearshore reef, the wave attenuation ability of the feature can be optimized Higher, wider and longer reefs provide the greatest barrier against wave energy but material volumes, navigation hazards, placement methods and other factors require engineering considerations for the overall design of the nearshore reefs.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.36 no.4
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• pp.457-463
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• 2012

Current refrigerators are designed to have thin doors and walls to facilitate user convenience and increase inner storage space. However, the thin doors and walls gives rise to the problem of dew generation on the outer surface of a refrigerator due to a large critical temperature difference between the outer wall and the room air; So far, an electric heater is commonly used for making the dew to evaporate; in this case, the heater inevitably requires additional electrical power. We propose a new approach to reduce the dew generation in a refrigerator by redesigning the gasket and varying the thickness of the inner case of the refrigerator. The results of simulations performed in this study indicate that the surface temperature in the region where dew was generated was increased by approximately $0.39{\sim}3.07^{\circ}C$ without the use of a heater.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.3
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• pp.8-14
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• 2012

Improving the speed of image processing is in great demand according to spread of high quality visual media or massive image applications such as 3D TV or movies, AR(Augmented reality). SIMD computer attached to a host computer can accelerate various image processing and massive data operations. MAMS is a multi-access memory system which is, along with multiple processing elements(PEs), adequate for establishing a high performance pipelined SIMD machine. MAMS supports simultaneous access to pq data elements within a horizontal, a vertical, or a block subarray with a constant interval in an arbitrary position in an $M{\times}N$ array of data elements, where the number of memory modules(MMs), m, is a prime number greater than pq. MAMS-PP4 is the first realization of the MAMS architecture, which consists of four PEs in a single chip and five MMs. This paper presents implementation of image processing algorithms and performance analysis for MAMS-PP16 which consists of 16 PEs with 17 MMs in an extension or the prior work, MAMS-PP4. The newly designed MAMS-PP16 has a 64 bit instruction format and application specific instruction set. The author develops a simulator of the MAMS-PP16 system, which implemented algorithms can be executed on. Performance analysis has done with this simulator executing implemented algorithms of processing images. The result of performance analysis verifies consistent response of MAMS-PP16 through the pyramid operation in image processing algorithms comparing with a Pentium-based serial processor. Executing the pyramid operation in MAMS-PP16 results in consistent response of processing time while randomly response time in a serial processor.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.10
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• pp.65-70
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• 2008

We design and fabricate the 94 GHz Coplanar waveguide(CPW)-to-rectangular waveguide transition that is transmits signal smoothly between the CPW, which is a popular transmission line of the planar circuits, and rectangular waveguide for the 94 GHz transceiver system. The proposed transition composed of the unilateral fin-line taper and open type CPW-to-slot-line transition is based on the hard and inflexible sapphire for the flip-chip bonding of the planar MMICs using conventional MMIC technology. We optimize a single section transition to achieve low loss by using an EM field solver of Ansoft's HFSS and fabricate the back- to-back transition that is measured by Anritsu ME7808A Vector Network Analyzer in a frequency range of $85{\sim}105$ GHz. From the measurement and do-embedding CPW with 3 mm length, an insertion and return loss of a single-section transition are 1.7 dB and more an 25 than at 94 GHz, respectively.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.20 no.5
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• pp.533-541
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• 2007

The Zienkiewicz-Zhu(Z/Z) error estimate is slightly modified for the hierarchical p-refinement, and is then applied to L-shaped plates subjected to bending to demonstrate its effectiveness. An adaptive procedure in finite element analysis is presented by p-refinement of meshes in conjunction with a posteriori error estimator that is based on the superconvergent patch recovery(SPR) technique. The modified Z/Z error estimate p-refinement is different from the conventional approach because the high order shape functions based on integrals of Legendre polynomials are used to interpolate displacements within an element, on the other hand, the same order of basis function based on Pascal's triangle tree is also used to interpolate recovered stresses. The least-square method is used to fit a polynomial to the stresses computed at the sampling points. The strategy of finding a nearly optimal distribution of polynomial degrees on a fixed finite element mesh is discussed such that a particular element has to be refined automatically to obtain an acceptable level of accuracy by increasing p-levels non-uniformly or selectively. It is noted that the error decreases rapidly with an increase in the number of degrees of freedom and the sequences of p-distributions obtained by the proposed error indicator closely follow the optimal trajectory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.