• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.113-118
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• 2016

In this paper, a read-in integrated circuit (RIIC) for IR scene projectors (IRSPs) adopting a sub-frame control technique is proposed, which minimizes the reduction of the apparent temperature of the IR images projected from IRSPs operating at a frame rate of 30 Hz. The proposed sub-frame control technique significantly reduces the amount of scene data loss on capacitors, which is caused by leakage currents flowing through MOSFET switches during holding periods, by dividing a unit frame into 8 sub-frames and refreshing the same scene data for each sub-frame. A current-drive RIIC was designed for the higher apparent temperature of IR radiated from the emitter, and it receives the scene data as a form of analog voltages from an external DAC. A prototype chip with a $64{\times}32$ RIIC array was fabricated using Magnachip/SKhynix $0.35{\mu}m$ 2-poly 4-metal CMOS process, and the measured maximum output data current is $230.3{\mu}A$. This amount of current ensures the projection of IR images whose maximum apparent temperature is $366.2^{\circ}C$ in the mid-wavelength IR (MWIR) when applied to a prototype emitter having a resistance of $15k{\Omega}$.

• Journal of Biomedical Engineering Research
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• v.22 no.5
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• pp.449-458
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• 2001

This is a test report of system efficiency for the moving-actuator type Bi-ventricular assist device (AnyHear $t^{MT}$ ) Seoul National University). $AnyHeart^{TM}$), as an energy converter. utilities a brushless DC motor(S/M 566-26A. Sierracin/ Magnedyne, Carlsbad, CA. U.S.A.) generating their pendulous motion in the epicyclic gear train. It is necessary to know about the overall efficiency of the system. The system is subdivided into three parts: motor part, actuator part and blood sac part (including valves, etc.) according to system mechanism. The motor was operated with a variable range of torque. angular speed and width of voltage Pulse In this report. $AnyHeart^{TM}$ is focused on the efficiency of the motor and actuator parts. 4 $\ell/min$ pump output. which is normal condition of $AnyHeart^{TM}$ system, the total system efficiency is 8%, which is composed of 50%, 85% and 17% efficiency (motor Part, actuator Part and blood sac Part) respectively. In the analyzed result. applied input voltage on normal condition of $AnyHeart^{TM}$ is determined. Also speed Profile with considering filling state of blood sac is Provided. In the test of the in vitro mock circulation. some experimental results are Provided to demonstrate the effectiveness of the Presented approach.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.119-125
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• 1990

This paper describes fiber optic voltage sensor using EOM-BSO (Electro-Optic Modulator-Bismuth Silicon Oxcide). Transceiver has an electical/optical converter and an optical/electrical converter which consist of light emitting diode, PIN-PD, and electronic circuits. Multimode fiber cable of $100/140{\mu}m$ core/clad diameter is used for connecting the transceiver to fiber cable and fiber optic voltage sensor. Before our experiments, by applying the Maxwell equations and wave equations, We derive matrix equation on wave propagation in the BSO single crystal. And also we derive optimal equation on intensity modulation arising through an analyzer. According to experi-mental results, fiber optic voltage sensor has maximum $2.5{\%}$ error within the applied AC voltage of 800V. As the applied voltage increases, saturation values of voltage sensor also increase. This phenomenon is caused by optical rotatory power of BSO single crystal. And temperature dependence of sensitivity for fiber optical rotatory power of BSO single crystal. And temperature dependence of sensitivity for fiber optic voltage sensor in the temperature range from$-20^{\circ}C\to\60^{\circ}C$ are measured within ${\pm}0.6{\%}$. And frequency characteristics of the voltage sensor has good frequency characteristics from DC to 100kHz.

• Journal of the Korean Magnetics Society
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• v.27 no.1
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• pp.1-8
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• 2017

Flywheel Energy Storage System (FESS) is composed by flywheel generating rotating potential energy and motor/generator set charging and discharging electric potential energy. The flywheel and motor/generator is connected by rotating shaft. And torque characteristics of motor/generator part can influence charging and mechanical traits of FESS. This paper analyze about motor/generator design method of 5 [kWh] FESS and torque ripple, harmonic effects by change of slots. At First, this paper proposes a method to estimate the flywheel size and the rotor size of the motor from the the rotational kinetic energy by inertia of FESS. The number of induction motor rotor slots for torque ripple reduction in the high speed operation region is selected. This paper performs to reduce the noise and vibration of the flywheel composed of coaxial with motor/generator and flywheel and realize the high efficiency.

• Korean Journal of Agricultural and Forest Meteorology
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• v.11 no.2
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• pp.61-71
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• 2009

Most deciduous trees in temperate zone are dormant during the winter to overcome cold and dry environment. Dormancy of deciduous fruit trees is usually separated into a period of rest by physiological conditions and a period of quiescence by unfavorable environmental conditions. Inconsistent and fewer budburst in pear orchards has been reported recently in South Korea and Japan and the insufficient chilling due to warmer winters is suspected to play a role. An accurate prediction of the flowering time under the climate change scenarios may be critical to the planning of adaptation strategy for the pear industry in the future. However, existing methods for the prediction of budburst depend on the spring temperature, neglecting potential effects of warmer winters on the rest release and subsequent budburst. We adapted a dormancy clock model which uses daily temperature data to calculate the thermal time for simulating winter phenology of deciduous trees and tested the feasibility of this model in predicting budburst and flowering of Niitaka pear, one of the favorite cultivars in Korea. In order to derive the model parameter values suitable for Niitaka, the mean time for the rest release was estimated by observing budburst of field collected twigs in a controlled environment. The thermal time (in chill-days) was calculated and accumulated by a predefined temperature range from fall harvest until the chilling requirement (maximum accumulated chill-days in a negative number) is met. The chilling requirement is then offset by anti-chill days (in positive numbers) until the accumulated chill-days become null, which is assumed to be the budburst date. Calculations were repeated with arbitrary threshold temperatures from $4^{\circ}C$ to $10^{\circ}C$ (at an interval of 0.1), and a set of threshold temperature and chilling requirement was selected when the estimated budburst date coincides with the field observation. A heating requirement (in accumulation of anti-chill days since budburst) for flowering was also determined from an experiment based on historical observations. The dormancy clock model optimized with the selected parameter values was used to predict flowering of Niitaka pear grown in Suwon for the recent 9 years. The predicted dates for full bloom were within the range of the observed dates with 1.9 days of root mean square error.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.98-106
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• 2009

This work proposes a 1280-RGB $\times$ 800-Dot 70.78mW 0.l3um CMOS LCD driver IC (LDI) for high-performance 16M-color low temperature poly silicon (LTPS) thin film transistor liquid crystal display (TFT-LCD) systems such as ultra mobile PC (UMPC) and mobile applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed LDI optimizes power consumption and chip area at high resolution based on a resistor-string based architecture. The single column driver employing a 1:12 MUX architecture drives 12 channels simultaneously to minimize chip area. The implemented class-AB amplifier achieves a rail-to-rail operation with high gain and low power while minimizing the effect of offset and output deviations for high definition. The supply- and temperature-insensitive current reference is implemented on chip with a small number of MOS transistors. A slew enhancement technique applicable to next-generation source drivers, not implemented on this prototype chip, is proposed to reduce power consumption further. The prototype LDI implemented in a 0.13um CMOS technology demonstrates a measured settling time of source driver amplifiers within 1.016us and 1.072us during high-to-low and low-to-high transitions, respectively. The output voltage of source drivers shows a maximum deviation of 11mV. The LDI with an active die area of $12,203um{\times}1500um$ consumes 70.78mW at 1.5V/5.5V.

• Journal of Intelligence and Information Systems
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• v.26 no.2
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• pp.1-25
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• 2020

In this paper, we suggest an application system architecture which provides accurate, fast and efficient automatic gasometer reading function. The system captures gasometer image using mobile device camera, transmits the image to a cloud server on top of private LTE network, and analyzes the image to extract character information of device ID and gas usage amount by selective optical character recognition based on deep learning technology. In general, there are many types of character in an image and optical character recognition technology extracts all character information in an image. But some applications need to ignore non-of-interest types of character and only have to focus on some specific types of characters. For an example of the application, automatic gasometer reading system only need to extract device ID and gas usage amount character information from gasometer images to send bill to users. Non-of-interest character strings, such as device type, manufacturer, manufacturing date, specification and etc., are not valuable information to the application. Thus, the application have to analyze point of interest region and specific types of characters to extract valuable information only. We adopted CNN (Convolutional Neural Network) based object detection and CRNN (Convolutional Recurrent Neural Network) technology for selective optical character recognition which only analyze point of interest region for selective character information extraction. We build up 3 neural networks for the application system. The first is a convolutional neural network which detects point of interest region of gas usage amount and device ID information character strings, the second is another convolutional neural network which transforms spatial information of point of interest region to spatial sequential feature vectors, and the third is bi-directional long short term memory network which converts spatial sequential information to character strings using time-series analysis mapping from feature vectors to character strings. In this research, point of interest character strings are device ID and gas usage amount. Device ID consists of 12 arabic character strings and gas usage amount consists of 4 ~ 5 arabic character strings. All system components are implemented in Amazon Web Service Cloud with Intel Zeon E5-2686 v4 CPU and NVidia TESLA V100 GPU. The system architecture adopts master-lave processing structure for efficient and fast parallel processing coping with about 700,000 requests per day. Mobile device captures gasometer image and transmits to master process in AWS cloud. Master process runs on Intel Zeon CPU and pushes reading request from mobile device to an input queue with FIFO (First In First Out) structure. Slave process consists of 3 types of deep neural networks which conduct character recognition process and runs on NVidia GPU module. Slave process is always polling the input queue to get recognition request. If there are some requests from master process in the input queue, slave process converts the image in the input queue to device ID character string, gas usage amount character string and position information of the strings, returns the information to output queue, and switch to idle mode to poll the input queue. Master process gets final information form the output queue and delivers the information to the mobile device. We used total 27,120 gasometer images for training, validation and testing of 3 types of deep neural network. 22,985 images were used for training and validation, 4,135 images were used for testing. We randomly splitted 22,985 images with 8:2 ratio for training and validation respectively for each training epoch. 4,135 test image were categorized into 5 types (Normal, noise, reflex, scale and slant). Normal data is clean image data, noise means image with noise signal, relfex means image with light reflection in gasometer region, scale means images with small object size due to long-distance capturing and slant means images which is not horizontally flat. Final character string recognition accuracies for device ID and gas usage amount of normal data are 0.960 and 0.864 respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

• Journal of the Korean Society of Propulsion Engineers
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• v.2 no.2
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• pp.74-82
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• 1998

Combined cycle power plant is a system where a gas turbine or a steam turbine is used to produce shaft power to drive a generator for producing electrical power and the steam from the HRSG is expanded in a steam turbine for additional shaft power. The temperature of the exhaust gases from a gas turbine ranges from $400{\sim}650^{\circ}C$, and can be used effectively in a heat recovery steam generator to produce steam. Combined cycle can be classed as a topping and bottoming cycle. The first cycle, to which most of the heat is supplied, is a Brayton gas turbine cycle. The wasted heat it produces is then utilized in a second process which operates at a lower temperature level is a steam turbine cycle. The combined gas and steam turbine power plant have been widely accepted because, first, each separate system has already proven themselves in power plants as an independent cycle, therefore, the development costs are low. Secondly, using the air as a working medium, the operation is relatively non- problematic and inexpensive and can be used in gas turbines at an elevated temperature level over $1000^{\circ}C$. The steam process uses water, which is likewise inexpensive and widely available, but better suited for the medium and low temperature ranges. It therefore, is quite reasonable to use the steam process for the bottoming cycle. Recently gas turbine attained inlet temperature that make it possible to design a highly efficient combined cycle. In the present study, performance analysis of a 3 pressured combined cycle power plant is carried out to investigate the influence of topping cycle to combined cycle performance. Present calculation is compared with acceptance performance test data from SeoInchon combined cycle power plant. Present results is expected to shed some light to design and manufacture 150~200MW class heavy duty gas turbine whose conceptual design is already being undertaken.