• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.37 no.8
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• pp.798-804
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• 2009

A high-resolution electro-optical camera system, EOS-C, is under development in Satrec Initiative. This system is the mission payload of a 400-kg Earth observation satellite. We designed this system to give improved opto-mechanical and thermal performance compared with a similar camera system to be flown on the DubaiSat-1 system. The thermal control subsystem (TCS) of the EOS-C system uses heaters to meet the opto-mechanical requirements during in-orbit operation and it uses different thermal coating materials and multi-layer insulation (MLI) blankets to minimize the heater power consumption. We performed its thermal analysis for the mission orbit using a thermal analysis model and the result shows that its TCS satisfies the design requirements.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.286-286
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• 2010

최근에 환경 오염과 화석 에너지의 고갈 문제를 해결하기 위하여 태양광을 전기 에너지로 변환하는 태양전지 연구에서 가장 이슈가 되는 부분은 저가격화와 고효율이다. 상용화 되어 있는 대부분의 태양전지는 단결정 실리콘 웨이퍼와 다결정 실리콘 웨이퍼를 사용한다. 실리콘 웨이퍼의 원자재 가격을 낮추는 방법에는 한계가 있기 때문에 태양전지 제작 공정에서 공정 단가를 낮추는 방법이 많이 연구되고 있고, 실리콘 웨이퍼가 가지는 재료의 특성상 화합물을 이용한 태양전지 보다 낮은 효율을 가질 수밖에 없기 때문에 반도체 소자 공정을 응용하여 실리콘 웨이퍼 기판에서 고효율을 얻는 방법으로 연구가 진행 되고 있다. 본 연구에서는 마이크로 블라스터를 이용하여 태양전지 cell 상부에 AG(anti-glare)를 가지는 유리 기판을 형성하여 낮은 단가로 태양전지 cell의 효율을 향상시키기 위한 연구를 진행 하였다. 태양전지 cell 상부에 AG를 가지는 유리 기판을 형성하게 되면 태양의 위도가 낮아 표면에서 대부분 반사되는 태양광을 태양전지 cell에서 광기전력효과가 일어나게 하여 효율을 향상시킨다. 이때 사용한 micro blaster 공정은 고속의 입자가 재료를 타격할 때 입자의 아래에는 고압축응력이 발생하게 되고, 이 고압 축응력에 의하여 소성변형과 탄성변형이 발생된다. 이러한 변형이 발전되어 재료의 파괴 초기값보다 크게 되면 크랙이 발생되고, 점점 더 발전하게 되면 재료의 제거가 일어나는 단계로 이루어지는 기계적 건식 식각 공정 기술이라 할 수 있다. 먼저 유리 기판에 마이크로 블라스터 장비를 이용하여 AG를 형성한다. AG는 $Al_2O_3$ 파우더의 입자 크기, 분사 압력, 노즐과 기판과의 간격, 반복 횟수, 노즐 이동 속도 등의 공정 조건에 따른 유리 기판 표면에서의 광학적 특성 및 구조적 특성에 관하여 분석하였다. 일반적인 태양전지 cell 제작 공정에 따라 cell을 제작 한후 AG 유리 기판을 상부에 형성시키고 솔라시뮬레이터를 이용하여 효율을 측정하였다. 이때 솔라시뮬레이터의 광원이 고정되어 있기 때문에 태양전지 cell에 기울기를 주어 태양의 위도 변화에 대해 간접적으로 측정하였다. AG 유리 기판이 태양전지 cell 상부에 형성 되었을 때와 없을 때를 각각 비교하여 AG 유리 기판이 형성된 태양전지 cell에서의 효율 향상을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.20-27
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• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.36 no.9
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• pp.1065-1071
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• 2012

Wind energy is becoming one of the most preferable alternatives to conventional sources of electric power that rely on fossil fuels. For stable electric power generation, constant rotating speed control of a wind turbine is performed through pitch control and stall control of the turbine blades. Recently, variable pitch control has been implemented in modern wind turbines to harvest more energy at variable wind speeds that are even lower than the rated one. Although wind turbine pitch controllers are currently optimized using a step response via the Ziegler-Nichols auto-tuning process, this approach does not satisfy the requirements of variable pitch control. In this study, the variable pitch controller was optimized by a genetic algorithm using a neural network model that was constructed by the Latin Hypercube sampling method to improve the Ziegler-Nichols auto-tuning process. The optimized solution shows that the root mean square error, rise time, and settle time are respectively improved by more than 7.64%, 15.8%, and 15.3% compared with the corresponding initial solutions obtained by the Ziegler-Nichols auto-tuning process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.50-57
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• 2009

This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.178-184
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• 2015

This paper proposes a hardware architecture for high performance Deblocking filter(DBF) in High Efficiency Video Coding for UHD(Ultra High Definition) videos. This proposed hardware architecture which has less processing time has a 4-stage pipelined architecture with two filters and parallel boundary strength module. Also, the proposed filter can be used in low-voltage design by using clock gating architecture in 4-stage pipeline. The segmented memory architecture solves the hazard issue that arises when single port SRAM is accessed. The proposed order of filtering shortens the delay time that arises when storing data into the single port SRAM at the pre-processing stage. The DBF hardware proposed in this paper was designed with Verilog HDL, and was implemented with 22k logic gates as a result of synthesis using TSMC 0.18um CMOS standard cell library. Furthermore, the dynamic frequency can process UHD 8k($7680{\times}4320$) samples@60fps using a frequency of 150MHz with an 8K resolution and maximum dynamic frequency is 285MHz. Result from analysis shows that the proposed DBF hardware architecture operation cycle for one process coding unit has improved by 32% over the previous one.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.755-758
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• 2014

In this paper, we propose effective Deblocking Filter hardware architecture for High Efficiency Video Coding encoder. we propose Deblocking Filter hardware architecture with less processing time, filter ordering for low area design, effective memory architecture and four-pipeline for a high performance HEVC(High Efficiency Video Coding) encoder. Proposed filter ordering can be used to reduce delay according to preprocessing. It can be used for realtime single-port SRAM read and write. it can be used in parallel processing by using two filters. Using 10 memory is effective for solving the hazard caused by a single-port SRAM. Also the proposed filter can be used in low-voltage design by using clock gating architecture in 4-pipeline. The proposed Deblocking Filter encoder architecture is designed by Verilog HDL, and implemented by 100k logic gates in TSMC $0.18{\mu}m$ process. At 150MHz, the proposed Deblocking Filter encoder can support 4K Ultra HD video encoding at 30fps, and can be operated at a maximum speed of 200MHz.