• The Transactions of the Korea Information Processing Society
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• v.6 no.7
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• pp.1929-1940
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• 1999

In this paper a VLSI design for the automatic magnetizing and inspection system has been presented. This is a design of a peripheral controller, which magnetizes CRTs and computer monitors and controls the automatic inspection system. We implemented a programmable peripheral interface(PPI) circuit of the control and protocol module for the magnetizer controller by using a 0.8um CMOS SOG technology of ETRI. Most of the PPI functions have been confirmed. In the conventional method, the propagation/ramp delay model was used to predict the delay of cells, but used to model on only a single cell. Later, a modified "linear delay predict model" was suggested in the LODECAP(LOgic DEsign CAPture) by adding some factors to the prior model. But this has not a full model on the delay chain. In this paper a new " delay predict equation" for the design of the timing control block in PPI system has been suggested. We have described the detail method on a design of delay chain block according to the extracted equation and applied this method to the timing control block design. And we had descriptions on the other blocks of this system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.67-75
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• 2004

This paper presents a buffer insertion method for RLC-class interconnect structured as a sin91e line or a tree. First, a closed form expression for the interconnect delay of a CMOS buffer driving single RLC line is represented. This expression has been derived by the n-th power law for deep submicrometer technology and occurs to be within 9 percentage of maximal relative error in accuracy compared with the results of HSPICE simulation for various RLC loads. This paper proposes a closed form expression based on this for the buffer insertion of single RLC lines and the buffer sizing algorithms for RLC tree interconnects to optimize path delays. The proposed buffer insertion algorithms are applied to insert buffers for several interconnect trees with a 0.25${\mu}{\textrm}{m}$ CMOS technology and the results are compared against those of HSPICE.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.81-89
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• 2000

In this paper, we analyzed the performance for CATV/LAN added priority problem. Upstrea nm channel which analyzed very deeply for CATV/LAN network have the preferential access property depending upon that positionand unidirectional property. To solve that fairness problem and priority, we propose the CSMA-CD/U/P-P protocolthat transmit as P1 probability if data packets happen. We assumed 2-Class priority(high, low). As the analyticresult and simulation, we obtained P1, value and its average delay time under priority problem assumed twoscenarios. Also, we get its variance value and queue length. Especially, the mean delay time increases nearer thanposition from H/E

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• autumn
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• pp.17-22
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• 2001

"대가지급"은 시공자(계약상대자)가 계약의 이행을 통해 얻고자 하는 궁극적인 목적이므로 "대가지급"과 관련된 계약조건은 발주자와 시공자 모두에게 공정하고 합리적인 내용이 되어야 할 것인데 우리나라 건설계약에 적용되고 있는 "공사계약일반조건(회계예규 2200.04-104-9, 2001.2.10)"에 규정된 "대가지급" 관련 조항의 내용은 그러한 합리성이 결여되어 있는 문제점이 있다. 대표적인 문제점으로 발주자가 대가지급을 하지 못하거나 지연시키는 경우 지급지연에 따른 이자에 대한 보상규정만을 두고 있을 뿐인데 이는 국제건설계약에 적용되고 있는 계약조건에 규정된 시공자의 권리와는 너무도 큰 차이가 있다 할 것이다. 그러므로 본 고에서는 세계건설시장에서 공정성과 합리성을 인정받고 있는 FIDIC 계약조건에 규정된 "대가지급" 관련 조항의 내용들을 구체적으로 알아보고 이를 통해 우리나라 건설계약에 적용되고 있는 계약조건의 문제점을 파악함으로써 건설제도의 선진화에 일조 하고자 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6B
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• pp.586-592
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• 2002

In this paper, new channel scheduling algorithms which reduce transmission delay caused by wireless network are proposed in AMC/TDM wireless data communication. The concept of the Proposed algorithms is based on the proportional fairness, M-LWDF, and performance-guaranteeing algorithm proposed by Xin Liu. The proposed algorithm can be applied to QoS guaranteeing services as well as best-effort services. Simulation results show that new algorithm reduced transmission delay upto 11.5% in case of proportional fairness algorithm and also decreased transmission delay unto 9% in case of M-LWBF algorithm.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2013.06a
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• pp.216-217
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• 2013

대형 조선소에서 하루 수십, 수백 개의 블록 이동이 있고 이동량이 많아지면 트랜스포터의 수, 운전기사, 신호수의 요구 증가를 야기해 비용 증가에 영향을 미친다. 또한 조선소에서 블록 이동은 공정 사이의 흐름에 영향을 미치며 전체 일정을 지연시킬 수도 있다. 그러므로 잘짜여진 블록 이동문제는 생산성 증가과 총 비용 감소에 있어 중요하다. 트랜스포터를 이용하여 블록을 이동하는데 트랜스포터란 고가의 특수운반차량으로 조선소에서 종류별(수백톤급)로 보유하고 있다. 트랜스포터는 가용 중량 이상의 블록을 이동할 수 없는데 이 때 두 대 이상의 차량을 결합하여 운반할 수 있다. 본 연구에서는 블록 무게와 트랜스포터의 적재 용량을 고려한 트랜스포터의 일정계획 문제를 다룬다. 계획된 공정 시간에 맞춰 블록이 도착할 수 있도록(지연시간 최소화)하는 모형을 정의하고 휴리스틱 알고리즘을 제안한다. 그리고 실험을 통해 최적화 모형과 휴리스틱 알고리즘의 효과를 검증하고자 한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.33-39
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• 2013

There have been studies in improving jitter characteristic of delay locked loop (DLL) even it has a shorter jitter that of phase locked loop (PLL). These studies result in numerous architectures of DLL which improve jitter performance. The paper shows that the jitter characteristic can be improved with various loop filters in DLL. It has been designed with 1.8V $0.18{\mu}m$ CMOS process.

• Electronics and Telecommunications Trends
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• v.32 no.1
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• pp.13-24
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• 2017

초저지연 인프라 기술은 인터넷 및 멀티미디어 정보 교환을 목적으로 만들어져 대역폭 증대에 힘써온 범용 통신망의 한계를 초월하여 실시간 시민감형 통신 및 산업 공정 제어 계측 정보 교환을 위하여 지연을 극소화 하고 확정할 수 있는 통신 인프라를 구축하기 위한 기술이다. 본고에서는 초저지연 인프라 구축을 위한 핵심 기술인 시간 제어 네트워크 기술과 전광 네트워킹 기술을 소개하고 산업 및 연구 기관의 관련 분야 활동 상황과 국제 표준화 동향에 대해 알아본다.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.16-21
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• 2006

This paper shows a vernier delay technique for generating precise multiphase clocks using PLL structure. The proposed technique can achieve the finer timing resolution less than the gate delay of the delay chain in VCO. Using this technique, 62.5ps of timing resolution can be achieved if the reference clock rate is set at 1GHz using 0.18um CMOS technology. Jitter of 14ps peak-to-peak was measured.

• Korean Journal of Construction Engineering and Management
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• v.12 no.6
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• pp.31-41
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• 2011

Since the cases of time extension have continuously transpired in the public construction project, the potential of economical loss and claims is increasing because the concerned parties such as an owner or a contractor have not properly performed their own responsibility for time extension. One of the main reasons is that the present planning and scheduling do not support the method to apportion the proper responsibility to the right party. This problem has repeatedly led to time extension and made it difficult for the concerned parties to perform the responsibility for time extension. In order to overcome this problem, a framework of delay administration is required as the method to apportion the proper responsibility to the right party. To solve this problem, this paper aimed to develop the conceptual model and prototype system as the practical method to administrate delay causation. Furthermore, the verification result for the reliability and applicability throughout the case studies on real construction projects shows that the conceptual model and prototype system developed would help efficiently to administrate the delay causation.