• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.105.1-105.1
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• 2010

바이오디젤 보급 활성화에 따른 식물성 원료유의 가격 상승 및 수급 불안정성 문제를 해결하고자 폐유지를 원료로 바이오디젤을 생산하고자 하는 시도가 이루어지고 있다. 폐유지의 사용은 폐자원 활용 측면에서 의미가 있으며 바이오디젤 생산 단가를 낮출 수 있다. 다양한 폐유지가 산업체로부터 배출되며 이 중에서 dark oil은 식용유 공장에서 식물성 원료유의 정제 과정에서 생기는 부산물로 바이오디젤로 전환 가능한 성분을 포함하고 있다. 본 연구에 사용된 dark oil은 54.9%의 유리지방산과 28.0%의 triglyceride, 4.4%의 diglyceride, 그리고 1% 이하의 monoglyceride를 함유하고 있다. Dark oil의 초기 산가는 109.8 mg KOH/g이었다. 본 연구에서는 dark oil의 유지 부분(triglyceride, diglyceride, monoglyceride)을 유리지방산으로 전환시켜 HAAO(high acid acid oil)을 생산한 후, 고체 산 촉매에 의한 에스테르화 반응을 통하여 바이오디젤을 생산하고자 하였다. 유지 부분의 유리지방산 전환 반응을 위하여 음이온성 계면활성제인 SDBS(sodium dodecyl benzene sulfonate)가 사용되었다. Dark oil:황산:물의 질량비가 10:2:10이고 SDBS가 오일 대비 3%인 조건에서 dark oil의 산가는 190.8 mg KOH/g까지 증가하였고, dark oil:황산:물의 질량비가 10:4:10이고 SDBS가 2%인 조건에서는 산가가 194.2 mg KOH/g까지 증가하였다. 생산된 HAAO을 이용하여 오일 대비 30%의 Amberlyst-15 촉매 하에서 HAAO:메탄올 몰비 1:9인 조건에서 에스테르화 반응을 수행하였을 경우 FAME(fatty acid methyl ester) 함량은 81.3%까지 증가하였다. 고체 산 촉매로써 Amberlyst-15와 가격 면에서 저렴한 PC101을 비교하였을 경우 FAME 함량은 각각 80.7%, 77.9%로 비슷한 효율을 나타내었다. 생산된 바이오디젤의 FAME 함량을 높이기 위해 증류 공정을 필요로 하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.23-30
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• 2012

This paper proposes a novel adaptive header-based power gating structure to compensate for the performance loss and the increased wake-up time of the power gating structures induced by the negative bias temperature instability (NBTI) effect. The proposed structure consists of variable width footers based on the two-pass power gating and a new NBTI sensing circuit for an adaptive control. The simulation results of the proposed structure are compared to those of power gating without the adaptive control and show that both the circuit-delay and wake-up time dependence of the power gating structure on the NBTI stress is minimized with only 3% and 4% increase, respectively while keeping small leakage power and rush-current. In this paper, a 45 nm CMOS technology and predictive NBTI model have been used to implement the proposed circuits.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.183-195
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• 2012

We propose a variable-latency Decimal Floating Point(DFP) adder which adopts the dual data path scheme. It is to speed addition and subtraction of operand that has identical exponents. The proposed DFP adder makes use of L. K. Wang's operand alignment algorithm, but operates through high speed data-path in guaranteed accuracy range. Synthesis results show that the area of the proposed DFP adder is increased by 8.26% compared to the L. K. Wang's DFP adder, though critical path delay is reduced by 10.54%. It also operates at 13.65% reduced path than critical path in case of an operation which has two DFP operands with identical exponents. We prove that the proposed DFP adder shows higher efficiency than L. K. Wang's DFP adder when the ratio of identical exponents is larger than 2%.

• KDI Journal of Economic Policy
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• v.18 no.1
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• pp.149-215
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• 1996

현행 민영화정책이 공기업의 효율성제고를 최우선 목표로 설정한 것은 타당한 선택이었음에도 불구하고, 경제력집중 심화에 대한 우려와 주식시장의 제약 등을 이유로 민영화정책은 그 추진실적이 부진하고 향후 지속 여부가 불투명한 것이 현실이다. 본(本) 논문(論文)은 우리나라 공기업민영화를 둘러싼 논쟁의 핵심인 경제력집중(經齊力集中), 경쟁도입(競爭導入), 주식시장여건(株式市場與件) 등이 공기업민영화와 관련하여 어떻게 이해되어야 할 것이며, 바람직한 정책대응(政策對應)은 무엇인지를 논의하고 있다. 재산권이론(財産權理論)을 동원하여 주인(主人) 있는 경영(經營)의 의미를 재해석할 때, 기업지배(企業支配) 통제구조(統制構造)의 정착이 요원한 우리 현실에서 민영화가 기업효율을 제고하려면 민간대주주(民間大株主)의 지배(支配)를 인정하는 방식이 최선책(最善策)이며, 소유가 분산되고 전문경영체제(專門經營體制)를 도입하는 민영화방식은 지배구조(支配構造)의 실패가능성(失敗可能性) 때문에 차선책(次善策)이라고 평가된다. 그러나 효율성 차원의 최선책은 경제력집중이라는 국민경제적 비용을 초래하므로, 정부로서는 경제력 집중이라는 비용(費用)과 효율성이라는 편익(便益)을 조화시키는 방안을 모색할 수밖에 없다. 이 경우 정부가 고려할 보완책(補完策)으로는 감자후(減資後) 민영화(民營化)와 분할민영화(分割民營化)가 있다. 한편 자연독점의 특성이 뚜렷한 일부 네트워크사업분야를 제외하면, 민영화시 경쟁도입(競爭導入)은 기업효율성과 국민경제의 배분효율성을 제고하므로 정부로서는 당연한 선택일 것이다. 경쟁은 공기업의 인수자격규제에 있어서도 새로운 기준을 제시하는데, 민영화를 정부(政府)와 민간(民間)사이의 M&A로 이해하고 경쟁제한적(競爭制限的) 기업결합(企業結合)을 규제하는 공정거래법(公正去來法)의 정신(精神)이 인수자격규제기준이 되어야 하며, 업종전문화(業種專門化) 발상(發想)에 근거한 인수자격규제는 득보(得)다 실(失)이 클 것이다. 아직도 자생적 성장기반이 취약한 주식시장의 제약에 따라 민영화일정의 탄력적인 조정은 불가피하지만, 정부는 상장(上場)의 필요성(必要性)을 재검토하고, 매각(賣却)의 우선순위(優先順位)를 조정하며, 무엇보다도 양질(良質)의 주식(柱式) 공급(供給)이 수요(需要)를 창출하는 메커니즘을 개발해야한다. 이와 함께 본(本) 논문(論文)은 현행 추진체계(推進體系)에 내재된 민영화의 지연가능성이 심각한 문제임을 지적하였고, 대규모 공기업의 민영화가 대기업(大企業)의 새로운 전형(典型)을 창출하여 한국자본주의(韓國資本主義)의 건전한 발전을 앞당기는 역사적 기회라는 점을 강조하고 있다. 마지막으로 재벌인수가 가능한 경우와 규제되어야 할 각각의 경우에 대하여 민영화정책(民營化政策)의 '체크리스트'를 제시하고 있다.

• Journal of Environmental Science International
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• v.27 no.1
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• pp.1-10
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• 2018

A continuous process of persulfate oxidation and citric acid washing was investigated for ex-situ remediation of complex contaminated soil containing total recoverable petroleum hydrocarbons (TRPHs) and heavy metals (Cu, Pb, and Zn). The batch experiment results showed that TRPHs could be degraded by $Fe^{2+}$ activated persulfate oxidation and that heavy metals could be removed by washing with citric acid. For efficient remediation of the complex contaminated soil, two-stage and three-stage processes were evaluated. Removal efficiency of the two-stage process (persulfate oxidation - citric acid washing) was 83% for TRPHs and 49%, 53%, 24% for Cu, Zn, and Pb, respectively. To improve the removal efficiency, a three-stage process was also tested; case A) water washing - persulfate oxidation - citirc acid washing and case B) persulfate oxidation - citric acid washing (1) - citric acid washing (2). In case A, 63% of TRPHs, 73% of Cu, 60% of Zn, and 55% of Pb were removed, while the removal efficiencies of TRPHs, Cu, Pb, and Zn were 24%, 68%, 62%, and 59% in case B, respectively. The results indicated that case A was better than case B. The three-stage process was more effective than the two-stage process for the remediation of complex-contaminated soil in therms of overall removal efficiency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.5
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• pp.397-400
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• 2018

This paper presents a miniaturized 65 nm CMOS 30~46 GHz wideband amplifier. To minimize the chip area, coupled inductors are used in the matching networks. The measurement shows that the fabricated amplifier exhibits 9.3 dB of peak gain, 16 GHz of 3 dB bandwidth, and 42 % fractional bandwidth. The measured input and output return losses were more than 10 dB at 35.8~46.0 GHz and 28.6~37.8 GHz, respectively. The chip consumes 42 mW at 1.2 V. The measured group delay variation is 19.1 ps within the 3 dB bandwidth and the chip size excluding the pads is $0.09mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.56-62
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• 2013

We present a rectifier for wireless power transmission using multiplier configuration in layout for MOSFETs which works at 13.56 MHz, designed to fit in CMOS process where conventionally used diodes are replaced with the cross-coupled MOSFETs. Full bridge rectifier structure without comparators is employed to reduce current consumption and to be working up to higher frequency. Multiplier configuration designed in layout reduces time delay originated from parasitic series resistance and shunt capacitance at each finger due to long connecting layout, leading to fast transition from on-state to off-state cross-coupled circuit structure and vice versa. The power conversion efficiency is significantly increased due to this fast transition time. The rectifier is fabricated in $0.11{\mu}m$ CMOS process, RF to DC power conversion efficiency is measured as 86.4% at the peak, and this good efficiency is maintained up to 600 MHz, which is, to our best knowledge, the highest frequency based on cross-coupled configuration.

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• autumn
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• pp.598-601
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• 2003

As the scale of construction work is enlarged, complicated and diversified, construction information from the large number of construction sites is happened and reported to the head office. To control much information generated in construction sites simultaneously, the necessity of supporting system which can extract necessary information is increased. However, compare with large companies, medium-sized companies's organization of head office and management system is weak, so it's difficult to manage multi-projects. Among these site managements, resource management is an important management area. But, resource planning is based on experience and judgement and have not associated with schedule information. So when schedule if changed, the plan must be amended manually. This study investigates material-planning model for multi-project management which is connected with daily report system and scheduling software.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.3
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• pp.537-548
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• 2000

ATM is the effective information transmission method which multiply statistical and can accept effective the traffic of the various transmission rate. However, it can happen excessive cell loss probability and cell delay when it have temporarily overload. Therefore, it is required the effective traffic control and network resource management for which guarantee QoS(Quality of Service) in terms of users and bandwidth utilization maximization in terms of networks. In this paper, we proposed POBP(PushOut BP) scheme which mixed pushout scheme with BP(Back Pressure), reactive control scheme recommended at the ATM Forum, to guarantee QoS in two stages ATM switch networks. In proposed method, we have to understand exactly using bandwidth information in real-time and become traffic shaping. Thorough these processes, we can not only use effectively unused bandwidth, but also guarantee the fair bandwidth utilization and then can improve cell-loss possibility happened by congestion states in two stage ATM networks.

• The KIPS Transactions:PartA
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• v.17A no.3
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• pp.121-126
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• 2010

This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The $16{\times}16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung $0.18\;{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.