• Korean Journal of Construction Engineering and Management
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• v.4 no.2 s.14
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• pp.74-81
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• 2003

In the construction industry, projects are becoming increasingly large and complex, involving multiple subcontractors. Traditional centralized coordination techniques used by the general contractors become less effective as subcontractors perform most wok and provide their own resources. When subcontractors cannot provide enough resources, they hinder their own performance as well as that of other subconractors and ultimately the entire project Thus, construction projects need a new distributed coordination approach wherein all of the concerned subcontractors can reschedule a project dynamically. To enable the distributed coordination framework of project schedule changes, the author developed an agent-based compensatory negotiation methodology, which allows intelligent software agents to simulate negotiations on behalf of their human subcontractors. In addition to this theoretical work, 1 designed and implemented a prototype to demonstrate the effectiveness of the framework. Thus, this research formalizes the necessary steps that would help construction project participants to increase the efficiency of their resource use, which in turn will enhance successful completions of whole projects.

• Korean Chemical Engineering Research
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• v.49 no.5
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• pp.565-570
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• 2011

In this paper, the analytical tuning rules of the proportional-integral-derivative (PID) controller have been derived for a broad class of stable, integrating, and unstable processes without time delay. On the basis of the renowned internal model control (IMC) design principles and the two-degree-of-freedom (2DOF) control structure, the proposed method can be effectively used for obtaining the enhanced performances of both the disturbance rejection as well as the set-point tracking problems, since the design scheme is simple, straightforward, and can be easily implemented in the process industry. Several processes without time delay are employed to demonstrate the improved closed-loop performance of the proposed controller design in compared with the other well-known design methods in terms of the same degree of robustness.

• Explosives and Blasting
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• v.32 no.3
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• pp.1-9
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• 2014

Since the rock fragmentation from a bench blasting can affect the subsequent processes including loading, hauling and crushing, its control is essential for the assessment of blasting efficiency as well as production cost. In this study, the delay time could be precisely controlled by using electronic detonators. The rock fragmentations resulted from the blastings with different delay times of 1, 2, 3, 4, 5, 7 and 10ms per each meter of burden were measured from full scale field tests in a limestone mine. The results showed that the optimum delay time for minimum fragmentation was approximately 6ms/m. From the analysis of fragmentation size distribution, it was possible to find that delay time can be a parameter on rock fragmentation and thus it would be possible to control rock fragmentation by adjusting delay time.

• Journal of Korea Multimedia Society
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• v.9 no.7
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• pp.844-853
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• 2006

The IEEE 802.17 Resilient Packet Ring (RPR) for future Local, Metropolitan, and Wide Area Networks was recently standardized, but it still suffer from delay jitter deterioration and even some bandwidth loss under unbalanced overload. In order to overcome these drawbacks, this paper proposes a bandwidth redistribution based fairness control method, compatible with the legacy one, in which each congested node measures the amount of available bandwidth of its bottleneck link resulted from regulating upstream nodes' shares of the link bandwidth, calculates optimal fair rate with the number of uptream nodes requiring more bandwidth, and then redistributes the available bandwidth to the upstream nodes by advertising the rate. The performance evaluation results show that the proposed method fairly redistributes 95% of the bottleneck link bandwidth with even only two redistributions.

• Proceedings of the Korean Aquaculture Society Conference
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• 2006.05a
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• pp.113-114
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• 2006

• Proceedings of the Korean Ceranic Society Conference
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• 2003.10a
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• pp.51-51
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• 2003

• Journal of the Korea Computer Industry Society
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• v.8 no.3
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• pp.197-206
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• 2007

The waiting delays of internet VOD users are inevitable in this policy since the services are not taken immediately upon requests but upon every scheduling points. An inefficient management of such delays makes an unfair service to users and increases the possibility of higher reneging rates. This paper proposes an efficient service scheduling scheme which improves the average waiting time of users requests and reduces the starvation problem of users requesting less popular movies. Experimental results of simulations show that the proposed scheme improves about 20 percentage of average waiting time and reduces significantly the starving requesters comparing with those of conventional methods such as FCFS and MQL.

• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.243-248
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• 2008

This paper proposes a low-power carry look-ahead adder using multi-threshold voltage CMOS. The designed adder is compared with conventional CMOS adder. The propagation delay time is reduced by using low-threshold voltage transistor in the critical path. Also, the power consumption is reduced by using high-threshold voltage transistor in the shortest path. The other logic block is implemented with normal-threshold transistor. Comparing with the conventional CMOS circuit, the proposed circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2378-2384
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• 2009

A novel phase-locked loop(PLL) architecture of sub-micron locking time has been proposed. Input frequency is multiplied by using a delay-locked loop(DLL). The input frequency of a PLL is multiplied while the PLL is out of lock. The multiplied input frequency makes the PLL having a wider loop bandwidth. It has been simulated with a $0.18{\mu}m$ 1.8V CMOS process. The simulated locking time is $0.9{\mu}s$ at 162.5MHz and 2.6GHz, input and output frequency, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.67-74
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• 2000

In this paper, a $54{\times}54$-bit multiplier based on a improved conditional sum adder is proposed. To reduce the multiplication time, high compression-rate compressors without Booth's Encoding, and a 108-bit conditional sum adder with separated carry generation block, are developed. Furthermore, a design technique based on pass-transistor logic is utilized for optimize the multiplication time and the power consumption by about 5% compared to that of conventional one. With $0.65{\mu}m$, single-poly, triple-metal CMOS process, its chip size is $6.60{\times}6.69\;mm^2$ and the multiplication time is 135.ns at a 3.3V power supply.