• Title/Summary/Keyword: 공정분할

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채권 전자거래 제도에 관한 연구

  • O, Seung-Hyeon
    • The Korean Journal of Financial Studies
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    • v.12 no.1
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    • pp.127-161
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    • 2006
  • 본 연구는 미국과 유럽의 채권 전자거래에 대한 제도를 분석한 후, 우리나라의 채권 전자거래에 대해 시사점을 제시하고자 한다. 본 연구의 결과는 다음과 같이 요약된다. 첫째, 미국과 유럽에선 채권 전자거래 시스템(Electronic Trading System, 이하 ETS)의 영업행위가 원칙적으로 증권 중개업의 관점에서 규제된다. 이러한 방향의 규제 체계는 다양한 형태의 채권 ETS가 등장할 수 있도록 하여 채권시장의 발전에 기여한다. 둘째, 우리나라의 $\ulcorner$한국증권선물거래소법$\lrcorner$ 15조 2항 및 $\ulcorner$증권거래법시행령$\lrcorner$ 84조의27 6항은 다양한 형태의 채권 ETS의 등장을 원천적으로 봉쇄함으로써 채권시장의 발전을 저해하고 있다. 셋째, 현행 $\ulcorner$한국증권선물거래소법$\lrcorner$ 15조 2항은 주식 및 선물거래에 대해서 계속 적용하되 채권거래에 대해서는 그 적용이 유보될 필요가 있다. 이를 통하여 $\ulcorner$한국증권선물거래소법$\lrcorner$은 주식시장을 활성화 시키는 순기능을 유지하면서 채권 ETS의 등장을 원천적으로 봉쇄하는 역기능을 피할 수 있다. 넷째, $\ulcorner$한국증권선물거래소법$\lrcorner$ 15조 2항이 채권거래에 대해서 적용되지 않는다면, $\ulcorner$증권거래법시행령$\lrcorner$ 84조의27 6항은 삭제되어야 하며, 대신에 증권거래법은 채권 ETS의 활동 범위와 요건을 정의해 주어야 한다. 채권 ETS의 활동은 원칙적으로 증권업자의 중개활동으로 간주되어야 한다. 채권 ETS의 중개 규모가 일정 수준을 넘어설 경우 거래소에 준하는 보고, 공시 및 감시 요건이 부과되는 것이 바람직하다. 다섯째, 채권시장의 효율성을 강화하기 위해서 채권 ETS에 대해서 적용되는 투명성 강화, 시장분할 방지, 공정거래 등에 대한 규제는 거래 대상의 특성에 따라서 탄력적으로 조정될 수 있어야 한다.

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Candida rugosa Lipase-Catalyzed Production of Optically Pure S-(+)-Ketoprofen (Candida rugosa 리파제를 이용한 광학적으로 순수한 S-(+)-Ketoprofen의 생산)

  • 김민곤;최순자;최원아;김철호;정봉현
    • KSBB Journal
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    • v.14 no.2
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    • pp.225-229
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    • 1999
  • Enzymatic resolution reactions were investigated using Candida rugosa lipase for the production of potically pure S-(+)-Ketoprofen. When the enzymatic hydroysis (and esterification) of recemic ketoprofen esters (and recemic ketoprofen with alcohol) was investigated comparatively, aqueous media was more specific for S-enantiomer than organic media. In the enzymatic hydrolysis of racemic ketoprofen ethyl ester in aqueous media, optimal temperature and pH for enantioselectivity were $37^{\circ}C$ and 4, respectively. The stereoselectivity of the enzyme was enhanced by adding dialcohols such as ethylene glycol and propylene glycol. The enantiomeric ratio obtained in the 40 %(v/v) ethylene glycol was 2-fold higher than that without the additive. By adding $CH_2Cl_2$, $CHCl_3$ and $CCl_4$ (5%,v/v), the enantioselectivity was reversed. A dramatic increase in the stereoselectivity was achieved using lipase purified by anion exchange chromatography. The type A lipase(the first eluted lipase fraction) showed an enantiomeric ratio of >100, whereas the type B lipase(the second eluted lipase fraction) exhibited enantimomer ratio of 9.0 in the hydrolysis of racemic ketoprofen ethyl ester.

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A Study on the Organic-Inorganic Multilayer Barrier Thin Films Using R2R Low-Temperature Atmospheric-Pressure Atomic Layer Deposition System (연속공정기반 저온 상압 원자층 증착 시스템을 이용한 유무기 멀티레이어 배리어 박막에 관한 연구)

  • Lee, Jae-Wook;Kim, Hyun-Bum;Choi, Kyung-Hyun
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.17 no.3
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    • pp.51-58
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    • 2018
  • In this paper, the organic material Poly(methyl methacrylate) PMMA is used with inorganic $Al_2O_3$ to fabricate organic-inorganic multilayer barrier thin films. The organic thin films are developed using a roll-to-roll electrohydrodynamic atomization system, whereas the inorganic are grown using a roll-to-roll low-temperature atmospheric pressure atomic layer deposition system. For the first time, these two technologies are used together to develop organic-inorganic multilayer barrier thin films in atmospheric condition. The films are grown under optimized parameters and classified into three classes based on the layer structures, when the total thickness of the barrier is maintained at ~ 160 nm. All classes of barriers show good morphological, optical and chemical properties. The $Al_2O_3$ films with a low average arithmetic roughness of 1.58 nm conceal the non-uniformity and irregularities in PMMA thin films with a roughness of 5.20 nm. All classes of barriers show a notably good optical transmission of ~ 85 %. The hybrid organic-inorganic barriers show water vapor and oxygen permeation in the range of ${\sim}3.2{\times}10^{-2}g/m^2/day$ and $0.015cc/m^2/day$ at $23^{\circ}C$ and 100% relative humidity. It has been confirmed that it can be mass-produced and used as a low-cost barrier thin film in various printing electronic devices.

Wireless Telemetry System for the FET-type Ion Sensors (FET형 이온센서용 무선원격측정시스템)

  • Jeong, H.;Choi, B.D.;Kim, Y.J.;Lee, Y.C.;Sohn, B.K.
    • Journal of Sensor Science and Technology
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    • v.10 no.3
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    • pp.187-195
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    • 2001
  • A wireless telemetry measurement system, using ISFETs, was developed for environmental monitoring applications, industrial processes, medical treatments and so on. This system is composed of the measurement part located at remote site and a personal computer(PC) which control whole instrument process. The measurement part transmits measured data to the PC by RF transceiver, and transmitted data are analyzed and handled in the PC. Proposed system utilizing time division multiplexing for the transmission of 3channel ISFET signal. The measurement part has an identification number(ID) so that the PC controls many measurement parts separately. Experiments were performed using pH-ISFETs, and the implemented system operates well within designed specification and accuracy of 0.1 pH.

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A 200-MHZ@2.5-V Dual-Mode Multiplier for Single / Double -Precision Multiplications (단정도/배정도 승산을 위한 200-MHZ@2.5-V 이중 모드 승산기)

  • 이종남;박종화;신경욱
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.4 no.5
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    • pp.1143-1150
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    • 2000
  • A dual-mode multiplier (DMM) that performs single- and double-precision multiplications has been designed using a $0.25-\mum$ 5-metal CMOS technology. An algorithm for efficiently implementing double-precision multiplication with a single-precision multiplier was proposed, which is based on partitioning double-precision multiplication into four single-precision sub-multiplications and computing them with sequential accumulations. When compared with conventional double-precision multipliers, our approach reduces the hardware complexity by about one third resulting in small silicon area and low-power dissipation at the expense of increased latency and throughput cycles. The DMM consists of a $28-b\times28-b$ single-precision multiplier designed using radix-4 Booth receding and redundant binary (RB) arithmetic, an accumulator and a simple control logic for mode selection. It contains about 25,000 transistors on the area of about $0.77\times0.40-m^2$. The HSPICE simulation results show that the DMM core can safely operate with 200-MHZ clock at 2.5-V, and its estimated power dissipation is about 130-㎽ at double-precision mode.

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Design of Graphic Memory for QVGA-Scale LCD Driver IC (QVGA급 LCD Driver IC의 그래픽 메모리 설계)

  • Kim, Hak-Yun;Cha, Sang-Rok;Lee, Bo-Sun;Jeong, Yong-Cheol;Choi, Ho-Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.12
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    • pp.31-38
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    • 2010
  • This paper presents the design of a graphic memory for QVGA-scale LCD Driver IC (LDI). The graphic memory is designed based on the pseudo-SHAM for the purpose of small area, and the memory cell structure is designed using a bit line partitioning method to improve sensing characteristics and drivabilties in the line-read operation. Also, a collision protection circuit using C-gate is designed to control collisions between read/write operations and self-refresh/line-read operations effectively. The graphic memory circuit has been designed in transistor level using $0.18{\mu}m$ CMOS technology library and the operations of the graphic memory have been verified using Hspice. The results show that the bit-bitb line voltage difference, ${\Delta}V$ increases by 40%, the charge sharing time between bit and bitb voltages $T_{CHGSH}$ decreases by 30%, and the current during line-read decreases by 40%.

Design of a 7-bit 2GSPS Folding/Interpolation A/D Converter with a Self-Calibrated Vector Generator (자체보정 벡터 발생기를 이용한 7-bit 2GSPS A/D Converter의 설계)

  • Kim, Seung-Hun;Kim, Dae-Yun;Song, Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.4
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    • pp.14-23
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    • 2011
  • In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

Design of a Doherty Power Amplifier Using the Spiral PBG Structure for Linearity Improvement (나선형 구조의 PBG를 적용한 도허티 전력증폭기의 선형성 개선)

  • Kim, Sun-Young;Seo, Chul-Hun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.45 no.1
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    • pp.115-119
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    • 2008
  • In this paper, the linearity of Doherty power amplifier has been improved by applying a new Photonic Bandgap(PBG) structure on the output of amplifier. The reposed spiral PBG structure is a two-dimensional(2-D) periodic lattice patterned on a dielectric slab that does not require nonplanar fabrication process. This structure has more broad stopband and high suppression performance than the conventional three cell PBG. Also, It has a sharp skirt property. We obtained the 3rd-order intermodulation distortion(IMD3) of -33dBc for CDMA applications with that of maintaining the constant power added efficiency(PAE), the IMD3 performance is improved as much as -8 dB compared with a Doherty power amplifier without PBG structure. Moreover, the physical length of PBG is shortened, therefore the whole amplifier circuit size is considerably reduced.

Design of a 2.5V 10-bit 300MSPS CMOS D/A Converter (2.5V 10-bit 300MSPS 고성능 CMOS D/A 변환기의 설계)

  • Kwon, Dae-Hoon;Song, Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.7
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    • pp.57-65
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    • 2002
  • In this paper, a 2.5V 10-bit 300MSPS CMOS D/A Converter is described. The architecture of the D/A Converter is based on a current steering 8+2 segmented type, which reduces non-linearity error and other secondary effects. In order to achieve a high performance D/A Converter, a novel current cell with a low spurious deglitchnig circuit and a novel inverse thermomeer decoder are proposed. To verify the performance, it is integrated with $0.25{\mu}m$ CMOS 1-poly 5-metal technology. The effective chip area is $1.56mm^2$ and power consumption is about 84mW at 2.5V power supply. The simulation and experimental results show that the glitch energy is 0.9pVsec at fs=100MHz, 15pVsec at fs=300MHz in worst case, respectively. Further, both of INL and DNL are within ${\pm}$1.5LSB, and the SFDR is about 45dB when sampling, frequency, is 300MHz and output frequency is 1MHz.

Efficient Resource Allocation to Support QoS in a Fixed Relay Based Cellular System (고정 릴레이 기반 셀룰러 시스템에서 QoS를 보장하기 위한 효율적인 자원 할당)

  • Kim, Geun-Bae;Shin, Hee-Young;Park, Sang-Kyu
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.10
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    • pp.1128-1135
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    • 2010
  • The relay based cellular system has been introduced to provide the service to satisfy the user requirement. The main reasons of using relay station are to expand a service coverage and to increase a system throughput with satisfying the service requirement level. This paper proposes a new resource allocation algorithm which supports the users' throughput fairness and service coverage in the Fixed Relay Based Cellular system with OFDMA. The performance of proposed algorithm is compared with the performances of proportional fairness(PF) algorithm. The simulation result shows that the proposed algorithm increases the number of active users in the service coverage while paying small amount of throughput loss.