• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.703-717
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• 2002

This paper illustrates the implementation of a scalable shared buffer asynchronous transfer mode (ATM) switch. The designed shared buffer ATM switch has a shared buffet of a pipelined memory which has the access time of 4 ns. The high-speed buffer access time supports a possibility of the implementation of a shared buffer ATM switch which has a large switching capacity. The designed switch architecture provides flexible switching performance and port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the designed ATM switch can be reconfigured without serious circuit redesign. The designed prototype chip has a shared buffer of 128-cell and 4 ${\times}$ 4 switch size. It is integrated in 0.6um, double-metal, and single-poly CMOS technology. It has 80MHz operating frequency and supports 640Mbps per port.

• Proceedings of the Korea Information Processing Society Conference
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• 2018.10a
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• pp.71-73
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• 2018

소프트웨어 애플리케이션의 가상화를 지원하는 컨테이너(container)는 일반적인 가상머신과 같은 운영체제의 격리된 인스턴스 형태이지만 VM과는 달리 호스트 OS자원을 공유하여 자원을 효율적으로 사용할 수 있고 이식성이 좋으며 배포를 쉽게 할 수 있는 등 장점이 있다. 컨테이너의 중요성과 활용도가 높아지면서 그것을 관리하고 통제하는 오케스트레이션 솔루션도 각광을 받고 있다. 본 논문에서는 Docker에 내장된 오케스트레이션 기능 중 하나인 Docker Swarm이 과도하게 메모리를 사용하는 문제점을 해결하고자 한다. 먼저, Docker Swarm의 구조에서 Manager 노드와 Worker 노드의 서비스를 증가시켜 실행시킨 후 성능을 평가한 후 과점유의 원인을 파악한다. 실험 결과 메모리 과점유의 원인은 컨테이너가 작동을 멈춘 후에도 여전히 메모리를 점유하고 있어 컨테이너를 증가시킬수록 메모리 이용률이 줄어들지 않는 것이 증명되었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1497-1501
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• 2005

Branch instructions which make the sequential instruction flow changed cause pipeline stalls in microprocessor. The pipeline hazard due to branch instructions are the most serious problem that degrades the performance of microprocessors. Branch target buffer predicts whether a branch will be taken or not and supplies the address of the next instruction on the basis of that prediction. If the hanch target buffer predicts correctly, the instruction flow will not be stalled. This leads to the better performance of microprocessor. In this paper, the architecture of a ta8 memory that branch target buffer and TLB can share is presented. Because the two tag memories used for branch target buffer and TLB each is replaced by single combined tag memory, we can expect the smaller chip size and the faster prediction. This shared tag architecture is more advantageous for the microprocessors that uses more bits of address and exploits much more instruction level parallelism.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.80-82
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• 1998

본 논문은 Mach 마이크로 커널 운영체제에서 네트웍 프로토콜과 운영체제의 오버헤드를 줄이는 사용자 수준의 프로토콜의 구현을 제시한다. 기존 사용자 수준의 프로토콜의 구현들은 그 성능에 있어서 커널 내 프로토콜의 그것에 비해 낮은 성능을 보여왔다. 이에 비해 본 논문에서는 더욱 더 높은 성능향상을 보이는 사용자 수준의 프로토콜 구조의 설계와 구현을 제시한다. 또한 Mach 의 공유 메커니즘을 쓴 사용자 프로토콜과 BSD UNIX 서버와의 공유 메모리를 사용하여 디스크에 저장된 파일을 네트웍 패킷으로 보낼 경우의 전송 능력을 향상시켰다. 이는 HTTP와 FTP 같이 최근 그 사용이 증대되고 있는 응용의 성능을 향상시킨다.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.08a
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• pp.85-88
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• 2000

장거리 링크를 가지는 ATM 망에서는 긴 전파지연의 영향을 고려하여 설정된 가상종단시스템을 이용하여 ABR 서비스를 제공해야 한다. 본 논문에서는 가상종단시스템을 이용하여 ABR 서비스를 제공하는 데에 필요한 조건인 많은 개수의 가상연결들에 대한 ABR 서비스 제어 기능을 설계하기 위한 제반 고려 사항들을 살펴보고 구현을 위한 설계 구조를 제시하였다. 제시한 설계 구조에서는 많은 개수의 가상연결들에 대해 ABR 서비스를 수용해 줄 수 있도록 공유 메모리 구조를 이용한 셀 송출 제어 구조를 적용하였다.

• Proceedings of the Korea Inteligent Information System Society Conference
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• 2007.11a
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• pp.353-356
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• 2007

로봇 시스템에서 지적 활동의 중심적 자료구조가 될 공유 메모리를 이용하여 로봇을 이루는 여러 Component Agent가 수집한 Context들과 산출된 Data들을 모아 Mental State를 구축한다. 로봇 Agent를 이루는 모든 컴포넌트들 간의 Data 교류는 Mental State를 통하여 일어나고, Reactive Layer와 Deliberative Layer로 구분 된 로봇을 구성하는 Agent들은 상황에 다라 변화된 context와 data값을 실시간으로 Mental State에 기록, 갱신한다. 이를 통하여 실시간 미션 수행 로봇이 효과적으로 목표를 수행할 수 있는 시스템 구조를 제시하고자 한다. 또한, 이러한 구조를 적용한 자가위치탐지 자율주행 로봇의 구현을 통해 본고에서 제시한 시스템 구조의 실현 가능성을 보이고자 한다.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.80-90
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• 2010

In this paper, we introduce some issues to implement an agent system to support service mobility in home network environment, and describe detailed design method in terminal as well as server agent. Specifically, we describe user recognition module, signaling message receiving/parsing module of terminal agent and signaling message receiving/parsing module, multimedia switching module, memory management module of server agent. We define several parameters managed in IP sharing device and design binding table structure to support mobility. And we utilize M/M/1/K queueing theory to obtain relations between memory size, blocking probability and memory utilization. From the obtained results, we show that memory size can be predicted in server agent mounted on IP sharing device.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.103-111
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• 2007

In this paper, we propose a VLSI architecture of hardware optimized high quality image signal processor for a Single-chip CMOS Image Sensor(CIS). The Single-chip CIS is usually used for mobile applications, so it has to be implemented as small as possible while maintaining the image quality. Several image processing algorithms are used in ISP to improve captured image quality. Among the several image processing blocks, demosaicing and image filter are the core blocks in ISP. These blocks need line memories, but the number of line memories is limited in a low cost Single-chip CIS. In our design, high quality edge-adaptive and cross channel correlation considered demosaicing algorithm is adopted. To minimize the number of required line memories for image filter, we share the line memories using the characteristics of demosaicing algorithm which consider the cross correlation. Based on the proposed method, we can achieve both high quality and low hardware complexity with a small number of line memories. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 37K, and seven and half line memories are used.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.1
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• pp.10-18
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• 2007

Mobile communication devices such as PDAs, cellular phones, etc., need to perform several kinds of computation-intensive functions including H.264 encoding/decoding and 3D graphics processing. In this paper, new reconfigurable architecture is described, which can perform either motion estimation for H.264 or rendering for 3D graphics. The proposed motion estimation techniques use new efficient SAD computation ordering, DAU, and FDVS algorithms. The new approach can reduce the computation by 70% on the average than that of JM 8.2, without affecting the quality. In 3D rendering, midline traversal algorithm is used for parallel processing to increase throughput. Memories are partitioned into 8 blocks so that 2.4Mbits (47%) of memory is shared and selective power shutdown is possible during motion estimation and 3D graphics rendering. Processing elements are also shared to further reduce the chip area by 7%.

• The KIPS Transactions:PartA
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• v.10A no.3
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• pp.231-238
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• 2003

Distributed systems present new system architecture for solving interoperability problem in heterogeneous system. This paper presents CORBA Inter-ORB protocol model based on shared memory to support communication software through analysis of existing CORBA IIOP protocol performance and Inter-Process Communication techniques. In the same host environment, proposed model applied standard CORBA mechanism to minimize message transfer overhead can develop software independently to hardware architecture of target communication system. This communication software that has flexibility and extensibility can improve productivity, duality and reusability of software.