• Title/Summary/Keyword: 공유 메모리 구조

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Design of Efficient frequency Offset Estimator for MB-OFDM based UWB Systems (MB-OFDM 기반 UWB 시스템을 위한 효율적인 주파수 옵셋 추정기의 설계)

  • Kim, Kil-Hwan;Jung, Yun-Ho;Kim, Jae-Seok
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.3C
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    • pp.311-321
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    • 2009
  • This paper proposes an efficient frequency offset estimation algorithm for MB-OFDM based UWB systems. The time-frequency interleaving in MB-OFDM extends the time-interval between two transmitted OFDM symbols in the same sub-band. The extended time-interval causes not only the degradation of the system performance by reducing frequency offset estimation range, but also the increase of the hardware complexity by requiring the larger number of storing samples. The proposed estimation algorithm expands the estimation range by applying the proposed sign detection scheme. Simulation results show that the estimation range is increased above 30 ppm compared with a conventional auto-correlation based scheme. The estimation is performed on only one sub-band, and the frequency offsets of the others are calculated by relation to center frequency. This way reduced the number of the storing samples by about l/3. The frequency offset estimator with the proposed algorithm was designed into the architecture which minimizes hardware overhead by time-sharing operators and memory units, and which was synthesized to gate-level circuits using $0.13{\mu}m$ CMOS technology, and the total gates were about 47K.

Distributed Intrusion Detection System for Safe E-Business Model (안전한 E-Business 모델을 위한 분산 침입 탐지 시스템)

  • 이기준;정채영
    • Journal of Internet Computing and Services
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    • v.2 no.4
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    • pp.41-53
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    • 2001
  • Multi-distributed web cluster model built for high availability E-Business model exposes internal system nodes on its structural characteristics and has a potential that normal job performance is impossible due to the intentional prevention and attack by an illegal third party. Therefore, the security system which protects the structured system nodes and can correspond to the outflow of information from illegal users and unfair service requirements effectively is needed. Therefore the suggested distributed invasion detection system is the technology which detects the illegal requirement or resource access of system node distributed on open network through organic control between SC-Agents based on the shared memory of SC-Server. Distributed invasion detection system performs the examination of job requirement packet using Detection Agent primarily for detecting illegal invasion, observes the job process through monitoring agent when job is progressed and then judges the invasion through close cooperative works with other system nodes when there is access or demand of resource not permitted.

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Accelerating Medical Image Processing on Integrated GPU Using OpenCL (OpenCL을 이용한 내장형 GPU에서의 의학영상처리 가속화)

  • Kim, Beom-Jun;Shin, Byeong-seok
    • Journal of the Korea Computer Graphics Society
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    • v.23 no.2
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    • pp.1-10
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    • 2017
  • A variety of filters are applied to improve the quality of noise and low resolution medical images. This is necessary to reduce the radiation dose of the patient and to improve the utilization of the conventional spherical imaging equipment. In the conventional method, it is common to perform filtering using the CPU of the PC. However, it is difficult to produce results in real time by applying various calculations and filters to high-resolution human images using only the CPU performance of a PC used in a hospital. In this paper, we analyze the structure and performance of Intel integrated GPU in CPU and propose a method to perform image filtering using OpenCL parallel processing function. By applying complex filters with high computational complexity to medical images, high quality images can be generated in real time.

Design and Implementation of a High Performance Web Crawler (고성능 웹크롤러의 설계 및 구현)

  • Kim Hie-Cheol;Chae Soo-Hoan
    • Journal of Digital Contents Society
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    • v.4 no.2
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    • pp.127-137
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    • 2003
  • A Web crawler is an important Internet software technology used in a variety of Internet application software which includes search engines. As Internet continues to grow, implementations of high performance web crawlers are urgently demanded. In this paper, we study how to support dynamic scheduling for a multiprocess-based web crawler. For high performance, web crawlers are usually based on multiprocess in their implementations. In these systems, crawl scheduling which manages the allocation of web pages to each process for loading is one of the important issues. In this paper, we identify issues which are important and challenging in the crawl scheduling. To address the issue, we propose a dynamic crawl scheduling framework and subsequently a system architecture for a web crawler with dynamic crawl scheduling support. This paper presents the design of the Web crawler with dynamic scheduling support.

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The Node Scheduling of Multi-Threaded Process for CC-NUMA System (CC-NUMA 시스템을 위한 다중 스레드 프로세스의 노드 스케줄링 설계 및 구현)

  • Kim, Jeong-Nyeo;Kim, Hae-Jin;Lee, Cheol-Hoon
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.2
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    • pp.488-496
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    • 2000
  • this paper describes the design and implementation of node scheduling for MX Server that is CC-NUMA System COMSIX, the operating system of MX Server, is designed to suit for CC-NUMA Architecture. MX Server consists of up to 8 nodes, and each node is connected by SCI ring. This node scheduling scheme considers data locality for performance improvement of Oracle8i DBMS on the CC-NUMA architecture. For DBMS such as Oracle8i, a multi-threaded process may be run to tie on particular disk. We have developed a CG binding function that the multi-threaded process bound the node. Currently, We don't have an available CC-NUMA Platform. Instead of MX Server, we developed the Node scheduling scheme for multi-threaded process to suit server platform on the PC test-bed and tested completely.

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A Target Manager for Remote Developments of Q+ Embedded Applications (내장형 소프트웨어의 원격 개발을 위한 Q+용 타겟관리자의 개발)

  • Lim, Chae-Deok;Lee, Woo-Jin;Son, Seung-Woo;Kim, Heung-Nam
    • Proceedings of the Korea Information Processing Society Conference
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    • 2000.04a
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    • pp.835-841
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    • 2000
  • 호스트와 타겟 간의 통신 부담과 타겟 자원이 제한적이라는 문제를 해결하기 위해서, 호스트 중심 원격 개발 환경(Remote Development Environment: RDE)을 구성하였다. 이 원격 개발 환경은 여러 개발 도구로 구성되어 있는데, 이들 도구가 타겟시스템에 접속하여 내장형 응용를 개발하는데 있어서 공통 기능, 공통 데이터가 존재한다. 그런데 이들을 각각 유지시키는 것은 타겟시스템에 부담을 줄 뿐만 아니라, 개발 도구를 추가/구현하는 것도 매우 어렵게 한다. 이 문제를 해결하기 위해 원격 개발 도구들의 공통 요소들을 모아 도구와 타겟시스템 사이에 중개자 역할을 하는 타겟관리자를 둔다. 타겟관리자는 미들웨어로서 호스트와 타겟 간의 통신 채널을 하나로 유지하면서 도구와 타겟 간의 통신을 중재하고, 도구들이 심볼 테이블을 공유할 수 있도록 심볼 테이블을 관리한다. 또한, 타겟에 있는 도구 전용 메모리를 관리하며, 호스트 상에서 개발한 내장형 소프트웨어를 타겟에 로딩하는 일을 처리한다. 이러한 타겟관리자를 사용하는 원격 개발 환경은 도구들에게 공통 인터페이스를 제공하여, 통신 방식 등의 하부 구조에 상관없이 서비스를 받을 수 있고, 새로운 도구를 추가하는 것도 용이하게 할 수 있다는 장점을 갖게 된다. 본 논문에서는 ETRI 에서 개발 중인 실시간 운영 체제인 Q+용 타겟관리자를 설계하고 구현한다. 또한, 타겟관리자가 동작하게 될 내장형 실시간 응용 개발 환경에 대하여 소개하고, 구현 결과를 도구들과 연계하여 보여주며, 타겟 관리자를 둔 원격 개발 환경이 타겟 관리자를 두지 않은 경우에 비해 호스트와 타겟 간의 통신 횟수가 얼마나 감소하는지 시험 결과를 통해 보여준다. 현재 타겟 관리자의 프로토타입을 개발하여 도구들과 통합 시험을 하였는데 기본 기능들이 성공적으로 수행됨을 확인하였다.

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A Performance Improvement of Linux TCP/IP Stack based on Flow-Level Parallelism in a Multi-Core System (멀티코어 시스템에서 흐름 수준 병렬처리에 기반한 리눅스 TCP/IP 스택의 성능 개선)

  • Kwon, Hui-Ung;Jung, Hyung-Jin;Kwak, Hu-Keun;Kim, Young-Jong;Chung, Kyu-Sik
    • The KIPS Transactions:PartA
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    • v.16A no.2
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    • pp.113-124
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    • 2009
  • With increasing multicore system, much effort has been put on the performance improvement of its application. Because multicore system has multiple processing devices in one system, its processing power increases compared to the single core system. However in many cases the advantages of multicore can not be exploited fully because the existing software and hardware were designed to be suitable for single core. When the existing software runs on multicore, its performance improvement is limited by the bottleneck of sharing resources and the inefficient use of cache memory on multicore. Therefore, according as the number of core increases, it doesn't show performance improvement and shows performance drop in the worst case. In this paper we propose a method of performance improvement of multicore system by applying Flow-Level Parallelism to the existing TCP/IP network application and operating system. The proposed method sets up the execution environment so that each core unit operates independently as much as possible in network application, TCP/IP stack on operating system, device driver, and network interface. Moreover it distributes network traffics to each core unit through L2 switch. The proposed method allows to minimize the sharing of application data, data structure, socket, device driver, and network interface between each core. Also it allows to minimize the competition among cores to take resources and increase the hit ratio of cache. We implemented the proposed methods with 8 core system and performed experiment. Experimental results show that network access speed and bandwidth increase linearly according to the number of core.

Design of Hardwired Variable Length Decoder for H.264/AVC (하드웨어 구조의 H.264/AVC 가변길이 복호기 설계)

  • Yu, Yong-Hoon;Lee, Chan-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.11
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    • pp.71-76
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    • 2008
  • H.264(or MPEG-4/AVC pt.10) is a high performance video coding standard, and is widely used. Variable length code (VLC) of the H.264 standard compresses data using the statistical distribution of values. A decoder parses the compressed bit stream and searches decoded values in lookup tables, and the decoding process is not easy to implement by hardware. We propose an architecture of variable length decoder(VLD) for the H.264 baseline profile(BP) L4. The CAVLD decodes syntax elements using the combination of arithmetic units and lookup tables for the optimized hardware architecture. A barral shifter and a first 1's detector parse NAL bit stream, and are shared by Exp-Golomb decoder and CAVLD. A FIFO memory between CAVLD and the reorder unit and a buffer at the output of the reorder unit eliminate the bottleneck of data stream. The proposed VLD is designed using Verilog-HDL and is implemented using an FPGA. The synthesis result using a 0.18um standard CMOS technology shows that the gate count is 22,604 and the decoder can process HD($1920{\times}1080$) video at 120MHz.

Cache Performance Analysis of Multiprocessor Systems for OLTP Applications based on a Memory-Resident DBMS (메모리 상주 DBMS 기반의 OLTP 응용을 위한 다중프로세서 시스템 캐쉬 성능 분석)

  • Chung, Yong-Wha;Hahn, Woo-Jong;Yoon, Suk-Han;Park, Jin-Won;Lee, Kang-Woo;Kim, Yang-Woo
    • Journal of KIISE:Computing Practices and Letters
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    • v.6 no.4
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    • pp.383-392
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    • 2000
  • Currently, multiprocessors are evaluated almost exclusively with scientific applications. Commercial applications are rarely explored because it is difficult to obtain the source codes of commercial DBMS. Even when the source code is available, such as for POSTGRES, understanding the source code enough to perform detailed meaningful performance evaluations is a daunting task for computer architects.To evaluate multiprocessors with commercial applications, we have developed our own DBMS, called EZDB. EZDB is a parallelized DBMS, loosely inspired from POSTGRES, and running on top of a software architecture simulator. It is capable of executing parallel programs written in SQL. Contrary to POSTGRES, EZDB is not intended as a prototype for a production-quality DBMS. Its purpose is to easily run and evaluate the performance of commercial applications on multiprocessor architectures. To illustrate the usefulness of EZDB, we showed the cache performance data collected for the TPC-B benchmark on a shared-memory multiprocessor. The simulation results showed that the data structures exhibited unique sharing characteristics and that their locality properties and working sets were very different from those in scientific applications.

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Design and Implementation of ISO/IEEE 11073 DIM Transmission Structure Based on oneM2M for IoT Healthcare Service (사물인터넷 헬스케어 서비스를 위한 oneM2M기반 ISO/IEEE 11073 DIM 전송 구조 설계 및 구현)

  • Kim, Hyun Su;Chun, Seung Man;Chung, Yun Seok;Park, Jong Tae
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.4
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    • pp.3-11
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    • 2016
  • In the environment of Internet of Things (IoT), IoT devices are limited by physical components such as power supply and memory, and also limited to their network performance in bandwidth, wireless channel, throughput, payload, etc. Despite these limitations, resources of IoT devices are shared with other IoT devices. Especially, remote management of the information of devices and patients are very important for the IoT healthcare service, moreover, providing the interoperability between the healthcare device and healthcare platform is essential. To meet these requirements, format of the message and the expressions for the data information and data transmission need to comply with suitable international standards for the IoT environment. However, the ISO/IEEE 11073 PHD (Personal Healthcare Device) standards, the existing international standards for the transmission of health informatics, does not consider the IoT environment, and therefore it is difficult to be applied for the IoT healthcare service. For this matter, we have designed and implemented the IoT healthcare system by applying the oneM2M, standards for the Internet of Things, and ISO/IEEE 11073 DIM (Domain Information Model), standards for the transmission of health informatics. For the implementation, the OM2M platform, which is based on the oneM2M standards, has been used. To evaluate the efficiency of transfer syntaxes between the healthcare device and OM2M platform, we have implemented comparative performance evaluation between HTTP and CoAP, and also between XML and JSON by comparing the packet size and number of packets in one transaction.