• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.34-42
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• 2014

This paper presents a low-complexity and high-throughput symbol detector for two-spatial-stream multiple-input multiple-output systems based on the modified maximum-likelihood symbol detection algorithm. In the proposed symbol detector, the cost function is calculated incrementally employing a multi-cycle architecture so as to eliminate the complex multiplications for each symbol, and the slicing operations are performed hierarchically according to the range of constellation points by a pipelined architecture. The proposed architecture exhibits low hardware complexity while supporting complicated modulations such as 256 QAM. In addition, various modulations and antenna configurations are supported flexibly by reconfiguring the pipeline for the slicing operation. The proposed symbol detector is implemented with 38.7K logic gates in a $0.11-{\mu}m$ CMOS process and its throughput is 166 Mbps for $2{\times}$3 16-QAM and 80Mbps for $2{\times}3$ 64-QAM where the operating frequency is 478 MHz.

• Journal of IKEEE
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• v.22 no.2
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• pp.233-241
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• 2018

This paper describes a lightweight implementation of a cryptographic processor supporting GCM (Galois/Counter Mode) authenticated encryption (AE) that is based on the two block cipher algorithms of ARIA and AES. It also provides five modes of operation (ECB, CBC, OFB, CFB, CTR) for confidentiality as well as the key lengths of 128-bit and 256-bit. The ARIA and AES are integrated into a single hardware structure, which is based on their algorithm characteristics, and a $128{\times}12-b$ partially parallel GF (Galois field) multiplier is adopted to efficiently perform concurrent processing of CTR encryption and GHASH operation to achieve overall performance optimization. The hardware operation of the ARIA/AES-GCM AE processor was verified by FPGA implementation, and it occupied 60,800 gate equivalents (GEs) with a 180 nm CMOS cell library. The estimated throughput with the maximum clock frequency of 95 MHz are 1,105 Mbps and 810 Mbps in AES mode, 935 Mbps and 715 Mbps in ARIA mode, and 138~184 Mbps in GCM AE mode according to the key length.

• Journal of the Korean School Mathematics Society
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• v.19 no.1
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• pp.1-19
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• 2016

This study investigated the mathematical notation used today in terms of skip ping the parenthesis. At first we have studied the elementary and secondary curriculum content related to omitted rules. As a result, it is difficult to find explicit evidence to answer that question 'What is the calculation of the $48{\div}2(9+3)$?'. In order to inquire the notation fundamentally, we checked the characteristics on prefix, infix and postfix, and looked into the advantages and disadvantages on infix. At the same time we illuminated the development of mathematical notation from the point of view of skipping the parenthesis. From this investigation, we could check that this interpretation was smooth in the point of view that skipping the parentheses are the image of the function. Through this we proposed some teaching methods including 'teaching mathematical notation based on historic genetic principle', 'reproduction of efforts to overcome the disadvantages of infix and understand the context to choose infix', 'finding the omitted parentheses to identify the fundamental formula' and 'specifying the viewpoint that skipping the multiplication notation can be considered as an image of the function'.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.106-114
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• 2016

In this paper, we propose an efficient integer inverse transform structure for vp9 decoder. The proposed structure is a hardware structure which is easy to control and requires less hardware resources, and shares algorithms for realizing entire DCT(Discrete Cosine Transform), ADST(Asymmetric Discrete Sine Transform) and WHT(Walsh-Hadamard Transform) in vp9. The integer inverse transform for vp9 google model has a fast structure, named butterfly structure. The integer inverse transform for google C model, unlike universal fast structure, takes a constant rounding shift operator on each stage and includes an asymmetrical sine transform structure. Thus, the proposed structure approximates matrix coefficient values for all transform mode and is used to matrix operation method. With the proposed structure, shared operations for all inverse transform algorithm modes can be possible with reduced number of multipliers compared to the butterfly structure, which in turn manages the hardware resources more efficiently.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.1
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• pp.139-149
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• 2010

Random scalar countermeasures, which carry out the scalar multiplication by the ephemeral secret key, against the differential power analysis of ECIES and ECDH have been known to be secure against various power analyses. However, if an attacker can find this ephemeral key from the one power signal, these countermeasures can be analyzed. In this paper, we propose a new power attack method which can do this analysis. Proposed attack method can be accomplished while an attacker compares the elliptic curve doubling operations and we use the principle component analysis in order to ease this comparison. When we have actually carried out the proposed power analysis, we can perfectly eliminate the error of existing function for the comparison and find a private key from this elimination of the error.

• Journal of Broadcast Engineering
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• v.15 no.2
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• pp.182-191
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• 2010

In this paper, a simple Carrier Frequency Recovery(CFR) scheme is introduced. In relating the use of consumer-grade equipment and satellite transmission environments, carrier frequency recovery have to recovery a large initial Carrier Frequency Offset(CFO), which is 20% normalized CFO, for DVB-S2 receivers. For these reasons, conventional CFR schemes for DVB-S2 systems need significant hardware complexity. Introduced CFR scheme employs Fitz algorithm for coarse CFR and recovers a coarse CFO accurately, and a simple pilot block correlation algorithm is employed for fine CFR. Introduced scheme reduce the number of multiplication operations by 80% and does not need any additional memory without degrading the achievable performance.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.54-61
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• 2008

This paper presents a new TIQ based CMOS flash 6-bit ADC to process digital signal in real time. In order to improve the conversion speed of ADC by designing new logic or layout of ADC circuits, a new design method is proposed in encoding logic circuits. The proposed encoding circuits convert analog input into digitally encoded double base number system(DBNS), which uses two bases unlike the normal binary representation scheme. The DBNS adopts binary and ternary radix to enhance digital arithmetic processing capability. In the DBNS, the addition and multiplication can be processed with just shift operations only. Finding near canonical representation is the most important work in general DBNS. But the main disadvantage of DBNS representation in ADC is the fan-in problem. Thus, an equal distribution algorithm is developed to solve the fan-in problem after assignment the prime numbers first. The conversion speed of simulation result was 1.6 GSPS, at 1.8V power with the Magna $0.18{\mu}m$ CMOS process, and the maximum power consumption was 38.71mW.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.6
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• pp.1401-1414
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• 2018

The k-means clustering algorithm groups input data with the number of groups represented by variable k. In fact, this algorithm is particularly useful in market segmentation and medical research, suggesting its wide applicability. In this paper, we propose a privacy-preserving clustering algorithm that is appropriate for outsourced encrypted data, while exposing no information about the input data itself. Notably, our proposed model facilitates encryption of all data, which is a large advantage over existing privacy-preserving clustering algorithms which rely on multi-party computation over plaintext data stored on several servers. Our approach compares homomorphically encrypted ciphertexts to measure the distance between input data. Finally, we theoretically prove that our scheme guarantees the security of input data during computation, and also evaluate our communication and computation complexity in detail.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.6
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• pp.125-134
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• 2004

When cryptosystem designers implement devices that computing power or memory is limited such as smart cards, PDAs and so on, not only he/she has to be careful side channel attacks(SCA) but also the cryptographic algorithms within the device has to be efficient using small memory. For this purpose, countermeasures such as Moiler's method, Okeya-Takagi's one and overlapping window method, based on window method to prevent SCA were proposed. However, Moiler's method and Okeya-Talngi's one require additional cost to prevent other SCA such as DPA, Second-Order DPA, Address-DPA, and so on since they are immune to only SPA. Also, overlapping window method has a drawback that requires big memory. In this paper, we analyze existing countermeasures and propose an efficient and secure countermeasure that is immune to all existing SCA using advantages of each countermeasure. Moreover, the proposed countermeasure can enhance the efficiency using mixed coordinate systems.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.463-471
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• 2021

Since 2016, National Institute of Standards and Technology (NIST) has been conducting a post quantum cryptography standardization project in preparation for a quantum computing environment. Three rounds are currently in progress, and most of the candidates (5/7) are lattice-based. Lattice-based post quantum cryptography is evaluated to be applicable even in an embedded environment where resources are limited by providing efficient operation processing and appropriate key length. Among them, SABER KEM provides the efficient modulus and Toom-Cook to process polynomial multiplication with computation-intensive tasks. In this paper, we present the optimized implementation of evaluation and interpolation in Toom-Cook algorithm of SABER utilizing ARM/NEON in ARMv8-A platform. In the evaluation process, we propose an efficient interleaving method of ARM/NEON, and in the interpolation process, we introduce an optimized implementation methodology applicable in various embedded environments. As a result, the proposed implementation achieved 3.5 times faster performance in the evaluation process and 5 times faster in the interpolation process than the previous reference implementation.