• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.4
• /
• pp.115-124
• /
• 2015

In this paper, the method which improves the performance of a serial decimal multiplier, and the method which operates multiple-digit simultaneously are proposed. The proposed serial decimal multiplier reduces the delay by removing encoding module that generates 2X, 4X multiples, and by generating partial product using shift operation. Also, this multiplier reduces the number of operations using multiple-digit operation. In order to estimate the performance of the proposed multiplier, we synthesized the proposed multiplier with design compiler with SMIC 110nm CMOS library. Synthesis results show that the area of the proposed serial decimal multiplier is increased by 4%, but the delay is reduced by 5% compared to existing serial decimal multiplier. In addition, the trade off between area and latency with respect to the number of concurrent operations in the proposed multiple-digit multiplier is confirmed.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.5 s.335
• /
• pp.23-30
• /
• 2005

In the construction of an extension field, there is a connection between the polynomial multiplication method and the degree of polynomial. The existing methods, KO and MSK methods, efficiently reduce the complexity of coefficient-multiplication. However, when we construct the multiplication of an extension field using KO and MSK methods, the polynomials are padded with necessary number of zero coefficients in general. In this paper, we propose basic properties of KO and MSK methods and algorithm that can reduce coefficient-multiplications. The proposed algorithm is more reducible than the original KO and MSK methods. This characteristic makes the employment of this multiplier particularly suitable for applications characterized by specific space constrains, such as those based on smart cards, token hardware, mobile phone or other devices.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.12 no.4
• /
• pp.1867-1875
• /
• 2011

In this paper, a low-area 256-point FFT structure is proposed. For low-area implementation CSD(Canonic Signed Digit) multiplier method is chosen. Because multiplication type should be less for efficient CSD multiplier application to the FFT structure, the Radix-$4^2$ algorithm is chosen for those purposes. After, in the proposed structure, the number of multiplication type is minimized in each multiplication block, the CSD multipliers are applied for implementation of multiplication. Furthermore, in CSD multiplier implementation, cell-area is more reduced through common sub-expression sharing(CSS). The Verilog-HDL coding result shows 29.9% cell area reduction in the complex multiplication part and 12.54% cell area reduction in overall 256-point FFT structure comparison with those of the conventional structure.

• Proceedings of the Korea Multimedia Society Conference
• /
• 2003.11a
• /
• pp.162-165
• /
• 2003

RSA 등의 공개키 암호화 시스템에서는 매우 큰 정수에 대해서 모듈러 멱승을 수행한다. 그러므로 모듈러 멱승을 효율적으로 구현하기 위하여 많은 연구가 진행되어 왔다. 모듈러 멱승을 소프트웨어적으로 구현할 경우 시간적인 제약을 극복하지 못하므로, 이를 하드웨어로 구현하려는 연구도 많이 이루어지고 있는 추세이다. 몽고메리 곱셈 알고리즘은 비용이 많이 드는 모듈러 연산을 효율적으로 처리하고 있으므로 하드웨어적 구현에 현재 널리 쓰이고 있다. 몽고메리 곱셈 알고리즘은 내부적으로 당연히 곱셈연산을 주로 사용하기 때문에, 어떤 곱셈기를 사용하느냐가 성능에 영향을 미치게 한다. 본 논문에서는 몽고메리 곱셈기를 다양한 32비트 곱셈기를 적용해 보고, 성능 및 면적을 측정하였다. 이러한 측정 결과를 토대로 특정 응용에 알맞은 32비트 곱셈기를 적절히 선택하여 설계할 수 있을 것으로 기대한다.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.3
• /
• pp.17-25
• /
• 1999

This paper proposes a new bit-serial multiplier/divider architecture to reduce the hardware complexity significantly and to maintain the same number of cycles compared with existing architectures. Since the proposed bit-serial multiplier/divider architecture does not extend the number of bits in registers and an adde $r_tractor to calculate a partial product or a partial remainder, the hardware overhead can be greatly reduced. In addition, the proposed architecture can perform an additio $n_traction and a shift operation in parallel and the number of cycles for $\textit{N}$-bit multiplication and division for the proposed circuits is $\textit{N}$ and $\textit{N}$ + 2, repectively. Thus, the number of cycles for multiplication and division is the same compared with existing architectures. The SliM Image Processor employs the proposed multiplier/divider architecture and proves the performance of the proposed architecture.cture.

• Proceedings of the Korean Information Science Society Conference
• /
• 2005.07a
• /
• pp.898-900
• /
• 2005

모듈러 멱승은 양수 x, E, N에 대하여 $x^Emod$ N로 정의된다. 모듈러 멱승 연산은 대부분의 공개키 암호화 알고리즘과 전자서명 프로토콜에서 핵심적인 연산으로 사용되고 있으므로, 그 효율성은 암호 프로토콜의 성능에 직접적인 영향을 미친다. 따라서 모듈러 멱승 연산에 필요한 곱셈 수를 감소시키기 위하여, 슬라이딩 윈도우를 적용한 CLNW 방법이나 VLNW 방법이 가장 널리 사용되고 있다. 본 논문에서는 조합론(combinatorics)에서 많이 응용되는 그래프 모델을 모듈러 멱승 연산에 적용할 수 있음을 보이고, 일반화된 그래프 모델을 통하여 VLNW 방법보다 더 적은 곱셈 수로 모듈러 멱승을 수행하는 방법을 설명한다. 본 논문이 제안하는 방법은 전체 곱셈 수를 감소시키는 새로운 블록들을 일반화된 그래프 모델의 초기 블록 테이블에 추가할 수 있는 초기 블록 테이블의 두 가지 확장 방법들로써, 접두사 블록의 확장과 덧셈 사슬 블록의 확장이다. 이 방법들은 새로운 블록을 초기 블록 테이블에 추가하기 위해 필요한 곱셈의 수와 추가한 뒤의 전체 곱셈 수를 비교하면서 초기 블록 테이블을 제한적으로 확장하므로, 지수 E에 non-zero bit가 많이 나타날수록 VLNW 방법에 비해 좋은 성능을 보이며 이는 실험을 통하여 검증하였다.

• Journal of Elementary Mathematics Education in Korea
• /
• v.23 no.1
• /
• pp.143-168
• /
• 2019

Along with the significance of algebraic thinking in elementary school, it has been recently emphasized that the properties of number and operations need to be explored in a meaningful way rather than in an implicit way. Given this, the purpose of this study was to analyze how third graders could understand the properties of operations in multiplication after they were taught such properties through a reconstructed unit of multiplication. For this purpose, the students from three classes participated in this study and they completed pre-test and post-test of the properties of operations in multiplication. The results of this study showed that in the post-test most students were able to employ the associative property, commutative property, and distributive property of multiplication in (two digits) × (one digit) and were successful in applying such properties in (two digits) × (two digits). Some students also refined their explanation by generalizing computational properties. This paper closes with some implications on how to teach computational properties in elementary mathematics.

• Proceedings of the Korean Information Science Society Conference
• /
• 2003.04a
• /
• pp.521-523
• /
• 2003

본 논문에서는 프로그램 가능한 셀룰라 오토마타(Programmable Cellular Automata, PCA)를 이용한 곱셈기를 제안한다. 본 논문에서 제안한 구조는 연산 후 늘어나는 원소의 수를 제한하기 위하여 이용되는 기약다항식(irreducible polynomial)으로서 All One Polynomial(AOP)을 사용하며, 주기적 경계 셀룰라 오토마타(Periodic Boundary Cellular Automata, PBCA)의 구조적인 특성을 사용함으로써 정규성을 높이고 하드웨어 복잡도와 시간 복잡도를 줄일 수 있는 장점을 가지고 있다. 제안된 곱셈기는 시간적. 공간적인 면에서 아주 간단히 구성되어 지수연산을 위한 하드웨어 설계나 오류 수정 코드(error correcting code)의 연산에 효율적으로 이용될 수 있을 것이다.

• Journal of KIISE:Computing Practices and Letters
• /
• v.15 no.4
• /
• pp.270-274
• /
• 2009

In this paper, we propose an efficient computation method over GF($2^m$) for memory-constrained devices. While previous methods concentrated only on fast multiplication, we propose to reduce the amount of required memory by cleverly changing the order of suboperations. According to our experiments, the new method reduces the memory consumption by about 20% compared to the previous methods, and it achieves a comparable speed with them.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.8
• /
• pp.1207-1212
• /
• 2013

Arithmetic operations over finite fields are widely used in coding theory and cryptography. In both of these applications, there is a need to design low complexity finite field arithmetic units. The complexity of such a unit largely depends on how the field elements are represented. Among them, representation of elements using a optimal normal basis is quite attractive. Using an algorithm minimizing the number of 1's of multiplication matrix, in this paper, we propose a multiplier which is time and area efficient over finite fields with optimal normal basis.