• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.10
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• pp.2123-2135
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• 1997

In this paepr, we consider resistive shorts on drain-source, drain-gate, and gate-source as well as opens in MOSFETs included in typical memory cell of VLSI SRAM. Behavior of memeory is observed by analyzing voltage at storage nodes of memeory and IDDQ(quiescent power supply current) through PSPICE simulation. Using this behavioral analysis, an effective testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ testing simultaeously is proposed. Built-In Self Test(BIST) circuit which detects faults in memories and Built-In Current Sensor(BICS) which monitors the power supply bus for abnormalities in quescent current are developed and imprlemented to improve the quality and efficiency of testing. Implemented BIST and BICS circuits can detect locations of faults and defects in order to repair faulty memories.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.711-714
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• 1998

본 논문에서는 wide data-width DRAM을 위한 flexible column redundancy scheme을 제안하였다. 구현된 redundancy scheme은 DB line shift method를 사용하여 wide data-width를 갖는 고집적 DRAM에 적용할 때 기존 redundancy scheme보다 더 작은 redundancy cell 면적과 fuse개수를 가지면서 더 큰 flexibility를 가지게 되었다.

• Journal of the KSME
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• v.54 no.5
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• pp.45-48
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• 2014

이 글에서는 최근 각광 받고 있는 기능성 소재 중 하나인 열전도성 폴리머 소재를 열교환기에 적용하기 위한 열유동 설계 기술에 대하여 논한다. 또한 폴리머열교환기가 기존 금속재질 열교환기와 비교하여 가지는 장단점을 살펴보고, 폴리머열교환기의 상용화 가능성에 대한 고찰을 하였다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2007.06a
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• pp.551-552
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• 2007

• Proceedings of the Korean Ceranic Society Conference
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• 2003.10a
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• pp.206.1-206
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• 2003

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.49-55
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• 2013

A high-voltage highly-integrated analog front-end (AFE) IC for medical ultrasound imaging applications is implemented using standard 0.18-${\mu}m$ CMOS process. The proposed AFE IC is composed of a high-voltage (HV) pulser utilizing stacked transistors generating up to 15 Vp-p pulses at 2.6 MHz, a low-voltage low-noise transimpedance preamplifier, and a HV switch for isolation between the transmit and receive parts. The designed IC consumes less than $0.15mm^2$ of core area, making it feasible to be applied for multi-array medical ultrasound imaging systems, including portable handheld applications.

• Journal of Broadcast Engineering
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• v.10 no.1 s.26
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• pp.77-82
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• 2005

We propose a highly Integrated motion estimation processor (MEP) for efficient video compression in an SoC platform. When compressing video by the standards like MPEG-4 and H.263, the macroblock related functions motion compensation. mode decision, motion vector prediction, and motion vector difference calculation require the frequent intervention of MCU. Thus the proposed MEP incorporates those functions with the motion estimation capability to reduce the number of interrupts to MCU, which can lead to a highly efficient SoC system. For low-power consumption, the proposed MEP can prevent the temporally static area from motion estimation or can skip the half-pel motion estimation for those macroblocks whose modes are decided as INTRA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.3
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• pp.573-579
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• 2001

The technology for characteristic analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high -integrated device by computer simulation and fabricate the device having such characteristics became one of very important subjects. As devices become smaller from submicron to nanometer, we have investigated MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane by TCAD(Technology Computer Aided Design) to develop optimum device structure. We analyzed and compared the EPI device characteristics such as impact ionization, electric field and I-V curve with those of lightly doped drain(LDD) MOSFET. Also, we presented that TCAD simulator is suitable for device simulation and the scaling theory is suitable at nano structure device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.490-493
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• 2000

The technology for characteristics analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high integrated device by computer simulation and to fabricate the device having such characteristics became one of very important subjects. As devices become smaller to submicron, we have investigated MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane by TCAD(Technology Computer Aided Design) to develop optimum device structure. We compared and analyzed the characteristics of such device structure, i.e., impact ionization, electric field and I-V characteristics curve with lightly-doped drain(LDD) MOSFET. Also, we presented that TCAD simulator is suitable for device simulation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.3
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• pp.1-5
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• 2011

In order to analyze the impedance properties of high integrated impedance network with multiple terminals, this paper introduces the concept of impedance relation matrix(IRM). The linear relation between the terminal voltages and currents is represented in the form of IRM and this matrix can be utilized to calculate the impedance between any two terminals. Furthermore, IRM representation for 2-port impedance network can be also defined. The whole impedance network is divided into the several 2-port sub-networks and each sub-network is analyzed in a form of the IRM representation. An illustrated example is given to show that the proposed method is simple and effective to analyze the impedance of a sensor array which has a very large number of impedance elements.