• Title/Summary/Keyword: 고정형 레이아웃

Search Result 2, Processing Time 0.017 seconds

The Implementation of an EPUB3.0-Based Fixed Layout e-Book (EPUB3.0 고정형 레이아웃 전자책 구현)

  • Moon, Hyun-Suk
    • Journal of Digital Contents Society
    • /
    • v.16 no.1
    • /
    • pp.105-112
    • /
    • 2015
  • The recent announcement of the EPUB3.0 e-book standard with enhanced features is expected to bring about much development and change to the production and circulation of e-books. This study thus set out to implement an EPUB3.0-based e-book containing various layout screens and interactive functions to stimulate readers' interest and investigate the production method considering the simultaneous publication of paper book and e-book. As for methodology and content, the investigator completed an edition and layout design and added an interactive function to it with Adobe Indesign CC(2014) and saved it as an EPUB3.0 file. She then opened the save EPUB file in the Sigil program, checked its specific codes and errors, and made revisions for its completion. The completed EPUB3.0 file was put to the test by installing four EPUB viewers, which were capable of implementing the EPUB3.0 features well based on the fitness results of epubtest.org and uploading files, in desktop and mobile devices. The present study claims its significance by implementing an EPUB3.0-based e-book capable of fixed layout and interactive features, cutting down the time and costs to make an e-book considerably by linking and using a production program, and proposing the possibility of simultaneous publication of paper book and e-book.

Design of Charge Pump Circuit for PLL (PLL을 위한 Charge Pump 회로 설계 및 고찰)

  • Hwang, Hongmoog;Han, Jihyung;Jung, Hakkee;Jeong, Dongsoo;Lee, Jongin;Kwon, Ohshin
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2009.05a
    • /
    • pp.675-677
    • /
    • 2009
  • 통신기기에서 중요한 기술 중 하나인 PLL(Phase Locked Loop) 회로는 주기적인 신호를 원하는 대로, 정확한 고정점으로 잡아주는데 그 목적을 둔다. 일반적인 구조로 위상주파수검출기(Phase Frequency detector), 루프필터(Loop filter), 전압제어발진기(Voltage Controlled Oscillator), 디바이더(Divider)로 구성되어진다. 그러나 일반적인 PLL 구조로는 지터(jitter)가 증가하고 트랙(tracking) 속도가 느리다는 단점이 있다. 이를 보완하기 위해 루프필터 전단에 차지펌프(Charge pump) 회로를 추가하여 사용하고 있다. 본 논문에서는 CMOS를 이용한 PLL용 차지펌프를 설계하였다. 설계된 회로는 $0.18{\mu}m$ CMOS 공정 기술을 사용하여 CADENCE사의 Specter로 시뮬레이션 하였으며, Virtuso2로 레이아웃 하였다.

  • PDF