• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1392-1400
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• 1999

In this paper, we propose a two-stage fast full search algorithm for block motion estimation that produces the same performance to that of full search algorithm (FSA) but with remarkable computation reduction. The proposed algorithm uses the search region subsampling and the difference of adjacent pixels in the current block. In the first stage, we subsample the search region by a factor of 9, and then calculate mean absolute error (MAE) at the subsampled search points. And in the second stage, we reduce the search points that need block matching process by using the lower bound of MAE value at each search Point. We Set the lower bound of MAE value for each search point from the MAE values which are calculated at the first stage and the difference of adjacent pixels in the current block. The experimental results show that we can reduce the computational complexity considerably without any degradation of picture quality.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.128-140
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• 2000

In this paper, we propose a fast block matching algorithm using the mean absolute error (MAE) of neighbor search point and search region reduction. The proposed algorithm is composed of two stages. At the first stage,the search region is divided into nonoverlapped 3$\times$3 areas and MAE of the center point of each area iscalculated. The minimum MAE value of all the calculated MAE's is determined as reference MAE. At thesecond stage, because the possibility that final motion vector exist near the position of reference MAE is veryhigh, we use smaller search region than first stage, And, using the MAE of center point of each area, the lowerbound of rest search point of each area is calculated and block matching process is performed only at the searchpoints that the lower bound is smaller than reference MAE. By doing so, we can significantly reduce thecomputational complexity while keep the increasement of motion estimation error small.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1970-1982
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• 1993

This paper describes an efficient array algorithm for parallel computation of vector-radix two-dimensional (2-D) fast discrete cosine transform (VR-FCT), and its VLSI implementation. By mapping the 2-D VR-FCT onto a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently importanted with high concurrency and local communication geometry. The proposed array algorithm features architectural modularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required, which is invitable in the conventional row-column decomposition approach. It has the time complexity of O(N+Nnzp-log2N) for (N*N) 2-D DCT, where Nnzd is the number of non-zero digits in canonic-signed digit(CSD) code, By adopting the CSD arithmetic in circuit desine, the number of addition is reduced by about 30%, as compared to the 2`s complement arithmetic. The computational accuracy analysis for finite wordlength processing is presented. From simulation result, it is estimated that (8*8) 2-D DCT (with Nnzp=4) can be computed in about 0.88 sec at 50 MHz clock frequency, resulting in the throughput rate of about 72 Mega pixels per second.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.1
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• pp.261-269
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• 2014

There are many researches on fast exponentiation algorithm which is used to implement a public key cryptosystem such as RSA. On the other hand, the malicious attacker has tried various side-channel attacks to extract the secret key. In these attacks, an attacker uses the power consumption or electromagnetic radiation of cryptographic devices which is measured during computation of exponentiation algorithm. In this paper, we propose a novel simple power analysis attack on m-ary exponentiation implementation. The core idea of our attack on m-ary exponentiation with pre-computation process is that an attacker controls the input message to identify the power consumption patterns which are related with secret key. Furthermore, we implement the m-ary exponentiation on evaluation board and apply our simple power analysis attack to it. As a result, we verify that the secret key can be revealed in experimental environment.

• The KIPS Transactions:PartC
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• v.8C no.1
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• pp.32-40
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• 2001

In this paper, we propose a high-speed modular multiplication algorithm which revises conventional Montgomery's algorithm. A hardware architecture is also presented to implement 1024-bit RSA cryptosystem for digital signature based on the proposed algorithm. Each iteration in our approach requires only one addition operation for two n-bit integers, while that in Montgomery's requires two addition operations for three n-bit integers. The system which is modelled in VHDL(VHSIC Hardware Description Language) is simulated in functionally through the use of $Synopsys^{TM}$ tools on a Axil-320 workstation, where Altera 10K libraries are used for logic synthesis. For FPGA implementation, timing simulation is also performed through the use of Altera MAX + PLUS II. Experimental results show that the proposed RSA cryptosystem has distinctive features that not only computation speed is faster but also hardware area is drastically reduced compared to conventional approach.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.6C
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• pp.585-593
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• 2007

For the improvement of coding efficiency, the H.264 standard uses new coding tools such as VBS, 1/4-pel accurate ME, multiple references, intra prediction, loop filter, etc. Using these coding tools, H.264 has achieved significant improvements from rate-distortion point of view compared to existing standards. However, the encoder complexity is greatly increased due to these coding tools. We focus on the complexity reduction method of intra-mode decision. Our algorithm first restricts selective prediction modes of Intra4x4 using a simple preprocessing. The prediction modes of Intra4x4 are used for restricting those of the other inter-modes. Simulation results show that the proposed method outperforms other conventional methods and save about 82% of total encoding time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2A
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• pp.128-139
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• 2004

As the Internet usage grows, people want to access the Internet while they are moving. To satisfy this requirement economically, IEEE 802.11 Wireless LANs(WLANs) are rapidly deployed. In order to support mobility, WLANs must provide smooth handoff mechanism. Recent studies show, however, handoff delay of WLANs exceeds 300ms, most of which is due to slow scanning mechanism finding a new AP. With this handoff delay, current WLANs is not suitable to provide seamless realtime interactive services such as VoIP sevice. In this paper, we analyze the current handoff method of IEEE 802.11 and we propose a new handoff algorithm which can decrease time needed for searching a new AP and thus reduce overall handoff time. We show by simulation that the proposed algorithm has shorter handoff delay than current handoff method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.5C
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• pp.548-554
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• 2003

Interoperability is ole the most important factors for a successful integration of the speech network. To accomplish communication between endpoints employing different speech coders, decoder and encoder of each endpoint coder should be placed in tandem. However, tandem coder often produces problems such as poor speech quality, high computational load, and additional transmission delay. In this paper, we propose an efficient transcoding algorithm that can provide interoperability to the networks employing ITU-T G.723.1［1］and TIA IS-127 EVRC［2］speech coders. The proposed transcoding algorithm is composed of four parts: LSP conversion, open-loop pitch conversion, fast adaptive codebook search, and fast fixed codebook search. Subjective and objective quality evaluation confirmed that the speech quality produced by the proposed transcoding algorithm was equivalent to, or better than the tandem coding, while it had shorter processing delay and less computational complexity, which is certified implementing on TMS320C62x.

• Proceedings of the Korea Multimedia Society Conference
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• 2004.05a
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• pp.379-382
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• 2004

적응신호처리 분야에서 LMS알고리듬은 수식이 간단하고, 적은 계산량으로 인해 널리 사용되고 있지만, 시간영역의 적응알고리즘은 입력신호의 고유치 분포폭이 넓게 분포한 때는 수렴속도가 느려지는 단점이 있다. 이런 문제점을 개선하기 위하여 본 논문에서는 시간영역의 적응 알고리즘을 변환영역에서 수행하고, 변환영역에서 수렴성능 향상과 계산량을 줄이기 위하여 웨이블렛기반의 고속 적응 알고리즘을 제안하였다. 제안한 알고리즘을 OFDM 적응등화기에 적용하여, 기존의 OFDM 등화기 알고리즘과 비교하여 제안한 적응알고리즘의 성능이 우수함을 보인다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1040-1046
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• 2004

The BLAST-OFDM system is an efficient method for high data rate multimedia transmission in futurewireless communication system. In this paper, a linear preceding mechanism and an efficient antenna-subcarrier assignment algorithm are proposed for the conventional BLAST-OFDM system, in order to utilize the full spatial diversity and the interleaved frequency diversity. By computer simulation, the proposed system has proved to achieve 4-5㏈ gain over the conventional BLAST-OFDM system.