• The Journal of the Acoustical Society of Korea
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• v.21 no.7
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• pp.648-655
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• 2002

This paper describes implementation of a multi-channel G.723.1 Annex A (G.723.1A) focused on code optimization using a high performance general purpose Digital Signal Processor (DSP), To implement a multi-channel G.723.1A functional complexities of the ITU-T G.723.1A fixed-point C-code are measures an analyzed. Then we sort and optimize C functions in complexity order. In parallel with optimization, we verify the bit-exactness of the optimized code using the ITU-T test vectors. Using only internal memory, the optimized code can perform full-duplex 17 channel processing. In addition, we further increase the number of available channels per DSP into 22 using fast codebook search algorithms, referred to as bit -compatible optimization.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.4
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• pp.333-337
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• 2004

This paper describe a design of 5GHz OFDM baseband chip for IEEE 802.11a wireless LAN. The proposed device is consists of transmitter and receiver within a single FPGA chip. We applied single tap equalizer that use Normalized LMS algorithm to remove ISI that happen at high speed data transmission. And also, we used carrier wave frequency offset algorithm that use training symbol to remove ICI. The simulation results show the correct transmission without errors the between transmitter and receiver And we can remarkably reduce the number of register through the synthesized circuits by using DSP block and EMB(Embedded Memory Block). The target device for implementation of the synthesized circuits is Altera Stratix EPIS25FC672 FPGA and design platform is VHDL.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.3
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• pp.275-281
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• 2014

Recently, the need for various underwater application systems targeting efficient resource exploration and aquatic ecosystem monitoring is rapidly increasing in littoral sea and inland waters. In this paper, we focus on the research and development of digital module of acoustic micro modem which can be used for underwater mobile communication systems and underwater sensor network systems. Specifically, a digital module of acoustic modem embedding digital signal processor is designed and implemented. On top of the developed hardware platform, physical layer frame generation and recovery and channel coding algorithms are mounted and tested in a water tank and a pond to verify its functionality and performance. According to experimental results, less than 1 percent of total computational power is consumed in the processing of frame control and convolutional code with the data rate of 1 kbps. Thus, the performance of micro modem could be improved by loading efficient baseband algorithms into the processor while maintaining the implemented hardware.

• The Journal of the Acoustical Society of Korea
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• v.35 no.3
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• pp.208-215
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• 2016

To control and improve a combustion behavior of an engine, various studies for the in-cylinder pressure have been consistently carried out. In this paper, the level of the combustion noise for a diesel engine is estimated from the in-cylinder pressure and defined as the combustion noise index. The combustion noise index is calculated from the FFT(Fast Fourier Transform) of the in-cylinder pressure and its validity is verified. The control system based on the combustion noise index is developed and implemented in a vehicle. A number of injection parameters are controlled to meet the desired combustion noise index, and the combustion noise of a vehicle is improved up to 4.0 dB(A) in the specified frequency band.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.9
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• pp.35-42
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• 1998

Finding a technique to achieve high machining precision and high productivity is an important issue for CNC machining. One of the solutions to meet better performance of machining is feedrate control. In this paper we present an adaptive feedrate neuro-control method for high precision and high speed machining. The adaptive neuro-control architecture consists of a neural network identifier(NNI) and an iterative learning control algorithm with inversion of the NNI. The NNI is an identifier for the nonlinear characteristics of feedrate and contour error, which is utilized in iterative learning for adaptive feedrate control with specified contour error tolerance. The proposed neuro-control method has been successfully evaluated for machining circular, corner and involute contours by computer simulations.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.132-139
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• 1989

We have designed a real-time Cardiac digital substraction angiography system (C-DSA) and tested the system for the diagnosis of Cardiac patients. The system was developed by interfacing a radiographic angiography system to a computerized motional image analysis system. This new cardiac DSA can perform the real time processing of averaging and subtraction of the 32 image frames to measure the volume changes of the left ventricle after elimination of motional artrifacts, caused by the heart contraction of beats per minute in average. Each frame has a resolution of 512 x 512 pixels and 256 gray levels. Two image data with maximal and minimal volume were moved to the interfaced IBM PC computer system by high speed computer link line for computation of the heart's contraction parameters. First, the boundary of the left ventricule was detected using a dynamic programming of the gray levels, and its volume was computered to determine the parameters, such as the maximal volume of end-diastolic volume (EDV), the minimal volume of end systolic volume (ESV), and ejection fraction (EF).

• Journal of Korea Multimedia Society
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• v.3 no.4
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• pp.356-364
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• 2000

Block based fast motion estimation algorithm use the fixed search pattern to reduce the search point, and are based on the assumption that the error in the mean absolute error space monotonically decreases to the global minimum. Therefore, in case of many local minima in a search region we are likely to find local minima instead of the global minimum and highly rely on the initial search points. This situation is evident in the motion boundary. In this paper we define the candidate regions within the search region using the motion information of the neighbor blocks and we propose the multiple local search method (MLSM) which search for the solution throughout the candidate regions to reduce the possibilities of isolation to the local minima. In the MLSM we mark the candidate region in the search point map and we avoid to search the candidate regions already visited to reduce the calculation. In the simulation results the proposed method shows more excellent results than that of other gradient based method especially in the search of motion boundary. Especially, in PSNR the proposed method obtains similar estimate accuracy with the significant reduction of search points to that of full search.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2006.11a
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• pp.111-115
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• 2006

스케일러블 비디오 코딩(SVC, Scalable Video Coding)은 MPEG(Moving Picture Expert Group)과 VCEG (Video Coding Expert Group)의 JVT(Joint VIdeo Team)에 의해 현재 표준화 되고 있는 새로운 압축 표준 기술이며 시간, 공간 및 화질의 스케일러빌리티를 지원하기 위해 계층 구조를 가지고 있다. 특히 시간적 스케일러빌리티를 위해 계층적 B-픽처 구조를 채택하고 있다. 스케일러블 비디오 코딩의 기본 계층은 H.264|AVC와 호환적이므로, 모션 예측과 모드 결정과정에서 $16{\times}16,\;16{\times}8,\;8{\times}16,\;8{\times}8,\;8{\times}4,\;4{\times}8$ 그리고 $4{\times}4$와 같은 7개의 서로 다른 크기를 갖는 블록을 사용한다. 스케일러블 비디오 코딩에서 사용되고있는 계층적 B-픽처 구조는 키 픽처인 I와 P 픽처를 제외하고는 한 GOP (Group of Picture)내에서 모두 B-픽처를 사용하므로 H.264|AVC와 비교했을 때 연산량 증가와 함께 부호화 지연도 급격히 증가한다. B-픽처는 양방향 모션 벡터인 LIST0와 LIST1을 사용하고 양방향 모두에서 다중 참조 픽처를 사용하기 때문이다. 본 논문에서는 통계적 가선 검증을 이용하여 스케일러블 비디오 부호화에 적용 가능한 고속 프레임간 모드 결정 알고리듬 대해 소개한다. 제안된 방법은 $16{\times}16$ 매크로 블록과 $8{\times}8$ 서브 매크로 블록에 통계적 가설 감증 기법을 적용하여 실행되며, 현재 블록과 복원된 참조 블록간의 픽셀 값을 비교하여 RD(Rate Distortion) 최적화 기반 모드 결정을 빨리 완료함으로써 고속 프레임간 모드 결정을 가능하게 한다. 제안된 방법은 프레임 간 모드 결정을 고속화함으로써 스케일러블 비디오 부호화기의 연산량과 복잡도를 최대 57%감소시킨다. 그러나 연산량 감소에 따른 비트율의 증가나 화질의 열화는 최대 1.74% 비트율 증가 및 0.08dB PSNR 감소로 무시할 정도로 작다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11C
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• pp.1029-1039
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• 2009

In this paper, the existing disparity aquisition algorithms were analyzed, on the bases of which a disparity generation technique that is superior in accuracy to the generation time was proposed. Basically it uses a pixel-by-pixel motion estimation technique. It has a merit of possibility of a high-speed operation. But the motion estimation technique has a disadvantage of lower accuracy because it depends on the similarity of the matching window regardless of the distribution characteristics of the texture in an image. Therefore, an enhanced technique to increase the accuracy of the disparity is required. This paper introduced a variable-sized window matching technique for this requirement. By the proposed technique, high accuracies could be obtained at the homogeneous regions and the object edges. A hardware to generate disparity image was designed, which was optimized to the processing speed so that a high throughput is possible. The hardware was designed by Verilog-HDL and synthesized using Hynix $0.35{\mu}m$ CMOS cell library. The designed hardware was operated stably at 120MHz using Cadence NC-VerilogTM and could process 15 frames per second at this clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.164-167
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• 2005

Recently, STC techniques have been considered to be candidate to support multimedia services in the next generation mobile radio communications and have been developed the many communications systems in order to achieve the high data rates. In this paper, we propose the Trellis-Coded Differential Space Time Modulation system with multiple symbol detection. The Trellis-code performs the set partition with unitary group codes. The Viterbi decoder containing new branch metrics is introduced in order to improve the bit error rate (BER) in the differential detection of the unitary differential space time modulation. Also, we describe the Viterbi algorithm in order to use this branch metrics. Our study shows that such a Viterbi decoder improves BER performance without sacrificing bandwidth and power efficiency.