• KIPS Transactions on Computer and Communication Systems
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• v.6 no.3
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• pp.105-112
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• 2017

PCI Express is a bus technology that connects the processor and the peripheral I/O devices that widely used as an industry standard because it has the characteristics of high-speed, low power. In addition, PCI Express is system interconnect technology such as Ethernet and Infiniband used in high-performance computing and computer cluster. PGAS(partitioned global address space) programming model is often used to implement the one-sided RDMA(remote direct memory access) from multi-host systems, such as computer clusters. In this paper, we design and implement a OpenSHMEM API based on PCI Express maintaining the existing features of OpenSHMEM to implement RDMA based on PCI Express. We perform experiment with implemented OpenSHMEM API through a matrix multiplication example from system which PCs connected with NTB(non-transparent bridge) technology of PCI Express. The PCI Express interconnection network is currently very expensive and is not yet widely available to the general public. Nevertheless, we actually implemented and evaluated a PCI Express based interconnection network on the RDK evaluation board. In addition, we have implemented the OpenSHMEM software stack, which is of great interest recently.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.6
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• pp.37-48
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• 2005

The efficiency of power supply circuits such as DC-DC converters and batteries varies on the trend of the power consumption because their efficiencies are not fixed. To analyze the efficiency of power supply circuits, we need the temporal behavior of the power consumption of the loads, which is dependent on the activity factors of the devices during the operation. Since it is not easy to model every detail of those factors, one of the most accurate power consumption analyses of power supply circuits is measurement of a real system, which is expensive and time consuming. In this paper, we introduce an active load emulator for embedded systems which is capable of power measurement, logging, replaying and synthesis. We adopt a pattern recognition technique for data compression in that long-term behaviors of power consumption consist of numbers of repetitions of short-term behaviors, and the number of short-term behaviors is generally limited to a small number. We also devise a heterogeneous structure of active load elements so that low-speed, high-current active load elements and high-speed, low-current active load elements may emulate large amount and fast changing power consumption of digital systems. For the performance evaluation of our load emulator, we demonstrate power measurement and emulation of a hard drive. As an application of our load emulator, it is used for the analysis of a DC-DC converter efficiency and for the verification of a low-power frequency scaling policy for a real-time task.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.12
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• pp.42-48
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• 2008

Next generation wireless communication systems require RF transceivers that enable multiband/multimode operations. Polar transmitters are known as good candidates for high data rate systems such as EDGE (Enhanced Data Rates for GSM Evolution), WCDMA (Wideband Code Division Multiple Access), and WLAN (Wireless Local Area Network) because they can obtain high efficiency by using efficient switched-mode RF power amplifiers. In this paper, we investigate the performance of a simple peak windowing scheme for the OFDM (Orthogonal frequency Division Multiplexing) polar transmitter, which requires no change of a receiver structure or no additional information transmission. The approach we employed is to apply the peak windowing scheme to the amplitude modulated signals of the polar transmitter to reduce the PAPR (Peak-to-Average Power Ratio). The BER (Bit Error Rate) and EVM (Error Vector Magnitude) performances are measured for various window types and lengths. The simulation results demonstrate that the proposed algorithm mitigates out-of-band distortion introduced by clipping along with PAPR reduction.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.10C
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• pp.967-983
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• 2003

In wireless spread-spectrum communication systems utilizing PN (pseudo noise) sequences, a variety of noise sources from the channel affect the data reception performance. Among them, in this paper we are concerned with the narrowband interference that may arise from the use of the spectral bands overlapped by the existing narrowband users or the intentional jammers as in military communication. The effect of this interference can be reduced to some extent at the receiver with the PN demodulation by processing gain. It is known, however, that when the interferers are strong, the reduction cannot be sufficient and thereby requiring the extra use of narrowband interference cancellers (NIC's) at the receivers. A class of adaptive NIC's are studied here based on different two cost functions. One is the chip mean-squared error (MSE) computed prior to the PN demodulation and used in the conventional cancellers. Since thses conventional cancellers should be operated at the chip rate, the computational requirements are enormous. The other is the symbol MSE computed after the PN demodulation in which case the weights of the NIC's can be updated at a lot lower symbol rate. To compare the performance of these NIC's, we derive a common measure of performance, i.e., the symbol MSE after the PN demodulation. The analytical results are verified by computer simulation. As a result, it is shown that the cancellation capability of the symbol-rate NIC's are similar or better than the conventional one while the computational complexity can be reduced a lot.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5B
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• pp.260-267
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• 2008

As pervious the SAR(Security Aware Routing)[10] protocol is an secure Ad Hoc network protocol that finds a secure path, it is the security routing protocol that uses the security level of nodes as the routing information. However, the SAR protocol sometimes transfers data through inefficient transmission paths because it always tries to find secure nodes for a safe transmission. Since it is a protocol based on AODV[6], it will cause transmission delay as researching of security routing path. when a node is out of the data transmission range as its battery dying or movement. Although it is possible to connection of nodes because a characteristic of the SAR protocol, the connection is not easy to reconnect when the security level of intermediate node is lower than the level requested by a source node. In this paper, we suggest the MP-SAR based on the SAR to solve the SAR protocol's problem. The MP-SAR seeks multiple secure path for maintenance of data confidentiality using the expanded secure path detection techniques based on the SAR. It can transfer data quickly and reliably by using the shortest efficient path among multiple paths. In the research result, we proved a outstanding performance of MP-SAR than the previous SAR through comparison and analysis.

• Journal of the Institute of Convergence Signal Processing
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• v.18 no.2
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• pp.55-61
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• 2017

In radio astronomy, high-capacity HDDs are being used to save huge amounts of HDDs in order to record the observational data. For VLBI observations, observational speeds increase and huge amounts of observational data must be stored as they expand to broadband. As the HDD is frequently used, the number of failures occurred, and then it takes a lot of time to recover it. In addition, if a failed HDD is continuously used, observational data loss occurs. And it costs a lot of money to buy a new HDD. In this study, we developed the integrity verification system of the Serial ATA HDD using FirmOS. The FirmOS is an OS that has been developed to function exclusively for specific purposes on a system having a general server board and CPU. The developed system performs the process of writing and reading specific patterns of data in a physical area of the SATA HDD based on a FirmOS. In addition, we introduced a method to investigate the integrity of HDD integrity by comparing it with the stored pattern data from the HDD controller. Using the developed system, it was easy to determine whether the disk pack used in VLBI observations has error or not, and it is very useful to improve the observation efficiency. This paper introduces the detail for the design, configuration, testing, etc. of the SATA HDD integrity verification system developed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1824-1832
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• 2011

In this paper, a smart home service robot McBot II is newly developed in much more practical and intelligent system than McBot I which we had developed a few years ago. Thus far, vacuum-cleaners have lightened the burden of household chores but the operational labor that vacuum-cleaners entail has been very severe. Recently, a cleaning robot was commercialized to solve but it also was not successful because it still had the problem of mess-cleanup, which pertained to the clean-up of large trash and the arrangement of newspapers, clothes, etc. Hence, we develop a new home mess-cleanup robot McBot II to completely overcome this problem on real environments. The mechanical design and the basic control of McBot II, which performs mess-cleanup function etc. in house, is actually focused in this paper. McBot II is mechanically modeled in the same method that the human works in door by using the waist and the hands. The big-ranged vertical lift and the shoulder joints to be able to forward move are mechanically designed for the operating function as the human's waist when the robot works. The mobility of McBot II is designed in the holonomic mobile robot for the collision avoidance of obstacle and the high speed navigation on the small area in door. Finally, good performance of McBot II, which has been optimally desinged, is confirmed through the experimental results for the control of the robotic body, mobility, arms and hands in this paper.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.5
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• pp.583-589
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• 2002

The Internet is absolutely contributed to information telecommunication revolution nowadays. Realizing local network at the various type of buildings such as a company and a university, ethernet is used for subnet and FDDI, ATM are used for backbone mainly in order to get internet services. Processing TCP/IP protocol suite and analyzing the protocol exactly is essential to detecting the problem occurring in the network and developing communication equipment. This paper presents implementation of ethernet LAN protocol analyser which monitors and simulates ICP/IP protocol suite carrying the Internet and non-Internet protocol such as Netware and NetBIOS. MS window98 and visual C are used for development environment and application program operates on the NDIS firmware. The performance analysis on the proposed system is carried out as monitoring and simulating the traffic over LAN of a university. In the result of monitoring the system, the processing time of a packet captured over the LAN is about 1.5ms. In case of simulating the system, the processing time to be taken carrying out TCP connection and disconnection once is packet is about 8.6ms. The performance analysis of monitoring and simulation results satisfies with 10 Mbps ethernet LAN environment.

• The KIPS Transactions:PartA
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• v.10A no.3
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• pp.247-254
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• 2003

This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.38 no.2
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• pp.211-218
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• 2014

Recently, software-based programmable logic controller (PLC) systems, which are implemented in standard PLC languages on general hardware, are gaining popularity because they overcome the limitations of classical hardware PLC systems. Another noticeable trend is that the use of integrated development environment (IDE) is becoming important. IDEs can help developers to easily manage the growing complexity of modern control systems. Furthermore, industrial Ethernet, e.g. EtherCAT, is becoming widely accepted as a replacement for conventional fieldbuses in the distributed control domain because it offers favorable features such as short transmission delay, high bandwidth, and low cost. In this paper, we implemented the extension of open source IDE, called Beremiz, for developing EtherCAT-based real-time, synchronized motion control applications. We validated the EtherCAT system management features and the real-time responsiveness of the control function by using commercial EtherCAT drives and evaluation boards.