• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.93-98
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• 2002

This paper introduces the design of high-speed analog-to-digital converter (ADC) for hard disk drive (HDD) read channel applications. This circuit is bated on fast regenerative autozero comparator for high speed and low-error rate comparison operation, and Double Speed Dual ADC (DSDA) architecture for efficiently increasing the overall conversion speed of ADC. A new type of thermometer-to-binary decoder appropriate for the autozero architecture is employed for no glitch decoding, simplifying the conventional structure significantly. This ADC is designed for 6-bit resolution, 800 Msample/s maximum conversion rate, 390 mW power dissipation, one clock cycle latency in 0.65 m CMOS technology.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.951-954
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• 2001

본 논문에서는 SDR (Software Defined Radio)시스템을 위한 디지털 IF (Intermediate Frequency)수신기를 구현하였다[1][2]. 구현된 수신기의 하드웨어 구조는 AD변환부, PDC(Programmable Down Converter)부, DSP (Digital Signal Processing)부분으로 이루어졌다. AD변환부는 Analog Devices사의 AD6644를 이용하여 아날로그 신호를14bit의 디지털 신호로 변환된다. PDC부분은 Intersil사의 HSP 50214B를 이용하여 14bit 샘플 된 IF(Intermediate Frequency)입력을 혼합기와 NCO(Numerically Controlled Oscillator)에 의해 기저대역으로 다운 시키는 역할을 한다. PDC는 CIC (Cascaded Integrator Comb)필터, Halfband 필터 그리고 프로그램할 수 있는 FIR필터로 구성되어 있다. 그리고 PDC부분을 제어하고 PDC부분에서 처리할 수 없는 캐리어, 심볼 트래킹을 위해 Texas Instrument사의 16비트의 고정소수점 DSP인 TMS320C5416과 Altera사의 FPGA를 사용하였다. 그러므로 중간주파수 대역과 기저대역 간의 신호변환을 디지털 신호처리를 수행함으로써 일반적인 아날로그 처리방식보다 고도의 유연성과 고성능 동작이 가능하고 시간과 환경 변화에 우수한 동작 특성을 제공한다.

• Journal of IKEEE
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• v.20 no.1
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• pp.61-67
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• 2016

In this paper, a hardware design method is proposed for high speed high precision neutron radiation measurements. Our system is fabricated to use a high performance A/D Converter for digital data conversion of high precision and high speed analog signals. Using a neutron sensor, incident neutron radiation particles are detected; a precision microcurrent measurement module is also included: this module allows for more precise and rapid neutron radiation measurement design. The high speed high precision neutron measurement hardware system is composed of the neutron sensor, variable high voltage generator, microcurrent precision measurement component, embedded system, and display screen. The neutron sensor detects neutron radiation using high density polyethylene. The variable high voltage generator functions as a 0 ~ 2KV variable high voltage generator that is robust against heat and noise; this generator allows the neutron sensor to perform normally. The microcurrent precision measurement component employs a high performance A/D Converter to precisely and swiftly measure the high precision high speed microcurrent signal from the neutron sensor and to convert this analog signal into a digital one. The embedded system component performs multiple functions including neutron radiation measurement for high speed high precision neutron measurements, variable high voltage generator control, wired and wireless communications control, and data recording. Experiments using the proposed high speed high precision neutron measurement hardware shows that the hardware exhibits superior performance compared to that of conventional equipment with regard to measurement uncertainty, neutron measurement rate, accuracy, and neutron measurement range.

• The Journal of the Acoustical Society of Korea
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• v.41 no.5
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• pp.507-517
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• 2022

The PhotoAcoustic Microscopy (PAM) has been proved to be a useful tool for biological and medical applications due to its high spatial and contrast resolution. PAM is based on transmission of laser pulses and reception of PA signals. Since the strength of PA signals is generally low, not only are high-performance optical and acoustic modules required, but high-performance electronics for imaging are also particularly needed for high-quality PAM imaging. Most PAM systems are implemented with a combination of several pieces of equipment commercially available to receive, amplify, enhance, and digitize PA signals. To this end, PAM systems are inevitably bulky and not optimal because general purpose equipment is used. This paper reports a PA signal receiving system recently developed to attain the capability of improved Signal to Noise Ratio (SNR) and Contrast to Noise Ratio (CNR) of PAM images; the main module of this system is a low noise, wideband signal receiver that consists of two low-noise amplifiers, two variable gain amplifiers, analog filters, an Analog to Digital Converter (ADC), and control logic. From phantom imaging experiments, it was found that the developed system can improve SNR by 6.7 dB and CNR by 3 dB, compared to a combination of several pieces of commercially available equipment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.47-55
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• 2005

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.11
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• pp.2649-2655
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• 2015

While the oversampling sigma-delta ADCs are known to have high resolution, they often suffer from SNDR losses when operated at a very high data clock. This paper presents a design and implementation of a decimation filter that provides minimum distortion at passband for high-speed sigma-delta ADC. The proposed digital decimation filter employs a butterworth structure. To evaluate the performance of the proposed decimation filter, we implemented a 1-bit, third-order, OSR=64 sigma-delta modulator followed by the proposed decimation filter. Using the simulation ad measurement, we compared the performance of the proposed decimation filter with a conventional CIC(cascaded integrator comb) decimation filter, which is commonly used in most sigma-delta ADCs. The measurement results show that the proposed decimation filter presents substantially lower distortion at passband and thus can provide must higher SNDR.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.1
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• pp.73-79
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• 2020

Modern radar system requires high spectral purity and low phase noise characteristics for very low RCS target detection and high resolution SAR (Synthetic Aperture Radar) image. This paper presents a new X-band high stable frequency synthesizer for high performance radar system, which combines DAS (Direct Analog Synthesizer) and DDS (Direct Digital Synthesizer) techniques, in order to cope with very low phase noise and high frequency agility requirements. This synthesizer offers more than 10% operating bandwidth in X-band frequency and fast agile time lower than 1 usec. Also, the phase noise at 10kHz offset is lower than -136dBc/Hz, which shows an improvement of more than 10dB compared to the current state of art frequency synthesizer. This architecture can be applied to L-band and C-band application as well. This frequency synthesizer is able to used in modern AESA (Active Electronically Scanned Array) radar system and high resolution SAR application.