• Journal of IKEEE
• /
• v.18 no.3
• /
• pp.305-312
• /
• 2014

IIt takes a lot of time and needs the workloads to verify the RTL code used in complex system like a nuclear control system which is required high level reliability using simple testbench. UVM has a layered testbench architecture and it is easy to modify the testbench to improve the code coverage. A test vector can be easily constructed in the UVM, since a constrained random test vector can be used even though the construction of testbench using UVM. We showed that the UVM testbench is easier than the verilog testbench for the analysis and improvement of code coverage.

• KIPS Transactions on Software and Data Engineering
• /
• v.6 no.5
• /
• pp.245-256
• /
• 2017

This paper proposes a method to generate test scripts for testing embedded system in an easy manner by using hierarchical checklist. In the proposed method, a checklist is constructed with event, component and command dictionaries. And the test scripts are hierarchically generated based on the dictionaries. Since the physical layer of system input becomes abstract with component layer and event layer by virtue of the hierarchy, It is possible to generate test scripts without complicated system input information. It is easy to generate test scripts for embedded systems with similar inputs using the highly reusable dictionaries. The effectiveness of the proposed method is demonstrated with experiments.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.2
• /
• pp.55-65
• /
• 2004

In this paper, An efficient non-scan DFT method for datapaths described in RTL is proposed. The proposed non-scan DFT method improves testability of datapaths based on hierarchical testability analysis regardless to width of the datapath. It always guarantees higher fault efficiency and faster test pattern generation time with little hardware overhead than previous methods. The experimental result shows the superiority of the proposed method of test pattern generation time, application time, and area overhead compared to the scan method.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.1
• /
• pp.52-60
• /
• 2003

For a System-on-a-Chip(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new flag based Wrapped Core Linking Module (WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2000.11b
• /
• pp.87-92
• /
• 2000

본 논문에서는 컨텍스트 기반 계층적 열거 부호화를 이용한 무손실 이진 영상 압축 알고리즘을 제안한다. 이진 영상내에 존재하는 인접한 화소간의 상호상관성을 이용하여 이진 영상을 1차원의 수열로 재구성하고, 이에 대해 계층적 열거 부호화를 실행한다. 제안하는 알고리즘은 덧셈 및 비교 연산만으로 구현이 가능하므로 그 복잡도가 매우 낮을 뿐만 아니라, CCITT 테스트 영상을 대상으로 한 부호화 성능 실험에서 우수한 성능을 나타낸다. 부호화 성능 비교에서 이진 영상 부호화 국제표준인 JBIG, G3, G4 및 GIF에 비해 우수한 압축 성능을 보인다.

• Journal of KIISE:Computing Practices and Letters
• /
• v.14 no.6
• /
• pp.547-558
• /
• 2008

Embedded system is tightly coupled with heterogeneous layers such as application, as kernel, device driver, HAL and hardware. Embedded system is customized for the specific purpose and hardware. In addition, the product cycle is so fast that software and hardware, which are developed by several vendors, are integrated together under unstable status. Therefore, there are lots of possibilities of faults in all layers. Because embedded software developers test their codes integrated with faulty layers, they cannot confirm 'whether testing of every aspects was completed, their code was failed, or integrated software/hardware has some problems'. In this paper, we propose an embedded software interface test method and a test tool called Justitia for detecting faults and tracing causes in the interface among heterogeneous layers. The proposed technique is an automated method which improves debugging upto professional testing using an emulator for helping developer.

• Journal of Korea Multimedia Society
• /
• v.5 no.1
• /
• pp.18-27
• /
• 2002

A hierarchical representation scheme for planar curves, MBO-tree, is proposed in this paper, which provides natural approximation and efficient localization. MBO-tree is based on the Douglas-Peucker algorithm (iterative end-point fit algorithm), but approximation errors that are stored with corresponding points in MBO-tree nodes and are used for abstraction measures are adjusted by force to eliminate unnatural approximation. The error adjusting is just making the approximation error of a node in a MBO-tree to be less than or equal to that of its parent. In point of localization, the bounding area of a curve is represented with a minimum bounding octangle (MBO), which can enclose the curve more compactly compared with those of other hierarchical schemes, such as the strip tree, the arc tree and the HAL tree. The MBO satisfies the hierarchical inclusion property that is useful for hierarchical geometrical operations, such as the point-inclusion test and the polygon intersection test. Through several experiments, we found that the proposed scheme was able to approximate more naturally and to localize more effectively.

• Review of KIISC
• /
• v.27 no.2
• /
• pp.46-56
• /
• 2017

사이버 물리 시스템(CPS, Cyber-Physical Systems)은 높은 신뢰성, 실시간성, 자동제어 특성이 요구되는 기반시설 제조 및 생산, 교통 등 산업분야에서 널리 쓰이고 있다. 센서와 액츄에이터 등의 현장장치를 네트워크 기반으로 일정한 상태를 유지하도록 제어를 담당하는 산업제어시스템이 그 예이다. 하지만, CPS는 네트워크 기반 상호 연결이 중가함에 따라 각종 사이버 공격이 급증하고 있는 추세이다. 이에 따라, CPS 보안 기술 연구의 필요성이 대두되었고, CPS 보안 기술 연구개발에 반드시 필요한 기반 환경으로써, 사이버영영과 물리영역을 포함하는 CPS 테스트베드 기술 연구가 활발히 진행 중에 있다. 본 논문에서는 CPS 관련 테스트베드 기술 동향 분석에 앞서 표준 및 지침에 명시된 CPS 구조에 대해 분석하고, 기존에 연구된 CPS 테스트베드 기술을 CPS의 계층적 구조를 기반으로 구성요소 및 구성방법을 비교 분석한다. 또한, CPS 테스트베드와 연계한 제어프로토콜 지원 현황과 사이버공격 시나리오 특징을 분석한다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.5
• /
• pp.54-64
• /
• 2002

Recently System On a Chip(SoC) design based on IP cores has become the trend of If design To prevent the testing problem from becoming the bottleneck of the core-based design, defining of an efficient test architecture and a successful test methodology are mandatory. This paper describes a test architecture and a test control access mechanism for SoC based on IEEE 1149.1 boundary,scan. The proposed SoC test architecture is fully compatible with IEEE P1500 Standard for Embedded Core Test(SECT), and applicable for both TAPed cores and Wrapped cores within a SOC with the same test access mechanism. Controlled by TCK, TMS, TDI, and TDO, the proposed test architecture provides a hierarchical test feature.

• Journal of KIISE:Software and Applications
• /
• v.36 no.11
• /
• pp.928-935
• /
• 2009

Ontology schema reasoning is used to maintain consistency of concepts and build concept hierarchy automatically. For the purpose, the search of concepts must be inevitably performed. Ontology schema reasoning performs the test of subsumption relationships of all the concepts delivered in the test set. The result of subsumption tests is determined based on the creation of complete graphs, which seriously weighs with the performance of reasoning. In general, the process of creating complete graph has been known as expressive procedure. This process is essential in improving the leading performance. In this paper, we propose a method enhancing the classification performance by identifying unnecessary subsumption test supported by optimized searching method on subsumption relationship test among concepts. It is achieved by propagating subsumption tests results into other concept.