• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국정보통신학회 2016년도 추계학술대회
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• pp.611-613
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• 2016

The characteristics of tunnel field-effect transistor(TFET) structure with source-overlapped gate was investigated using a TCAD simulations. Tunneling is mostly divided into line-tunneling and point-tunneling, and line-tunneling is higher performance than point-tunneling in terms of subthreshold swing(SS) and on-current. In this paper, from the simulation results of source-overlapped gate length effects at silicon(Si), germanium(Ge), Si-Ge hetero TFET structure, the guideline of optimal structure with highest performance are proposed.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제18권12호
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• pp.2939-2945
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• 2014

This paper has analyzed the change of threshold voltage for oxide structure of symmetric and asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET can be fabricated with different top and bottom gate oxide thickness, while the symmetric DGMOSFET has the same top and bottom gate oxide thickness. Therefore optimum threshold voltage is considered for top and bottom gate oxide thickness of asymmetric DGMOSFET, compared with the threshold voltage of symmetric DGMOSFET. To obtain the threshold voltage, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. We investigate for bottom gate voltage, channel length and thickness, and doping concentration how top and bottom gate oxide thickness influences on threshold voltage using this threshold voltage model. As a result, threshold voltage is greatly changed for oxide thickness, and we know the changing trend greatly differs with bottom gate voltage, channel length and thickness, and doping concentration.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제41권9호
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• pp.19-24
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• 2004

In this paper, we have demonstrated the fabrication of a 70 nm foot print of the T-gate by using a positive resist ZEP520/P(MMA-MAA)/PMMA trilayer by double exposure method without a thin dielectric supporting layer on the substrate. The device performance was characterized by DC and RF measurement. The fabricated 70 nm InGaAs/InAlAs MHEMTS with 70 ${\mu}{\textrm}{m}$ unit gate width and 2 fingers showed good DC and RF characteristics of Idss, max =228.6 mA/mm, gm =645 mS/mm, and fT =255 GHz, respectively.

• ETRI Journal
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• 제14권1호
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• pp.52-65
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• 1992

전자선 직접묘사 (E-beam direct writing lithography) 방법을 이용하여 $0.2\mum$ 과 $0.3\mum$ 의 게이트길이를 가지는 NMOS 트랜지스터를 제작하였다. 게이트만 전자선 직접묘사 방법으로 정의하고 나머지는 optical stepper를 이용하는 Mix & Match 방식을 사용하였다. 게이트산화막의 두께는 최소 6nm까지 성장시켰으며, 트랜지스터구조로서는 lightly-doped drain(LDD) 구조를 채택하였다. 짧은 채널효과 및 punch through를 줄이기 위한 방안으로 채널에 깊이 붕소이온을 주입하는 방법과 well을 고농도로 도핑하는 방법 및 소스와 드레인에 $p^-$halo를 이온주입하는 enhanced lightly-doped drain(ELDD) 방법을 적용하였으며, 제작후 성능을 각각 비교하였다. 제작된 $0.2\mum$의 게이트길이를 가지는 소자에서는 문턱전압과 subthreshold기울기는 각각 0.69V 및 88mV/dec. 이었으며, Vds=3.3V에서 측정한 포화 transconductance와 포화 드레인전류는 각각 200mS/mm, 0.6mA/$\mum$이었다. $0.3\mum$소자에서는 문턱전압과 subthreshold 기울기는 각각 0.72V 및 82mV/dec. 이었으며, Vds=3.3V에서 측정한 포화 transconductance는 184mS/mm이었다. 이러한 결과는 전원전압이 3.3V일 때 실제 ULSI에 적용가능함을 알 수 있다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.95-95
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• 2008

본 연구에서는 SiGe p-MOSFET을 제작하여 I-V 특성과 게이트 길이, $V_D$, $V_G$의 변화에 따른 저주파 노이즈특성을 측정하였다. Si 기판위에 성장한 $Si_{0.88}Ge_{0.12}$으로 제작된 SiGe p-MOSFET의 채널은 게이트 산화막과 20nm 정도의 Si Spacer 층으로 분리되어 있다. 게이트 산화막은 열산화에 의해 70$\AA$으로 성장되었고, 게이트 폭은 $25{\mu}m$, 게이트와 소스/드레인 사이의 거리는 2.5때로 제작되었다. 제작된 SiGe p-MOSFET은 빠른 동작 특성, 선형성, 저주파 노이즈 특성이 우수하였다. 제작된 SiGe p-MOSFET의 ESD 에 대한 소자의 신뢰성과 내성을 연구하기 위하여 SiGe P-MOSFET에 ESD를 lkV에서 8kV까지 lkV 간격으로 가한 후, SiGe P-MOSFET의 I-V 특성과 게이트 길이, $V_D$, $V_G$의 변화에 따른 저주파 노이즈특성 변화를 분석 비교하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제9권8호
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• pp.1749-1753
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• 2005

In this paper, we have investigated electrical characteristics by action temperature of double gate structure that have main gate and side gate. Could know current-voltage characteristic is superior in ultra low temperature (77 K) as well as in room temperature (300 K). Also, conditions of most suitable for get superior DG MOSFET's dynamic characteristics are main gate length of 50nm and side gate length of 70nm and could know that should be approved more than voltage 2V. Also, this DG MOSFET usefully use may as digital device because on-off characteristic is superior.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국정보통신학회 2014년도 춘계학술대회
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• pp.741-744
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• 2014

This paper has analyzed threshold voltage roll-off for bottom gate voltages of asymmetric double gate(DG) MOSFET. Since the asymmetric DGMOSFET is four terminal device to be able to separately bias for top and bottom gates, the bottom gate voltage influences on threshold voltage. It is, therefore, investigated how the threshold voltage roll-off known as short channel effects is reduced with bottom gate voltage. In the pursuit of this purpose, off-current model is presented in the subthreshold region, and the threshold voltage roll-off is observed for channel length and thickness with a parameter of bottom gate voltage as threshold voltage is defined by top gate voltage that off-currnt is $10^{-7}A/{\mu}m$ per channel width. As a result to observe the threshold voltage roll-off for bottom gate voltage using this model, we know the bottom gate voltage greatly influences on threshold voltage roll-off voltages, especially in the region of short channel length and thickness.

• Journal of the Korean Vacuum Society
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• 제15권6호
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• pp.637-641
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• 2006

We present the DC and RF characteristics of 100 nm gate length InGaAs/InAlAs/GaAs metamorphic high electron mobility transistors (MHEMTs). We fabricated the T-gate with 100 nm foot print by using a positive resist ZEP520/P (MMA-MAA)/PMMA trilayer by double exposure method. The fabricated 100 nm MHEMT with a $70\;{\mu}m$ unit gate width and two fingers were characterized through do and rf measurements. The maximum drain current density of 465 mA/mm and extrinsic transconductance $(g_m)$ of 844 mS/mm were obtained with our devices. From rf measurements, we obtained the current gain cut-off frequency $(f_T)$ of 192 GHz, and maximum oscillation frequency $(f_{max})$ 310 GHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국정보통신학회 2014년도 춘계학술대회
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• pp.755-758
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• 2014

This paper has analyzed the change of threshold voltage for oxide structure of symmetric and asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET can be fabricated with different top and bottom gate oxide thickness, while the symmetric DGMOSFET has the same top and bottom gate oxide thickness. Therefore optimum threshold voltage is considered for top and bottom gate oxide thickness of asymmetric DGMOSFET, compared with the threshold voltage of symmetric DGMOSFET. To obtain the threshold voltage, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. We investigate for bottom gate voltage, channel length and thickness, and doping concentration how top and bottom gate oxide thickness influences on threshold voltage using this threshold voltage model. As a result, threshold voltage is greatly changed for oxide thickness, and we know the changing trend very differs with bottom gate voltage, channel length and thickness, and doping concentration.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제19권7호
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• pp.1617-1622
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• 2015

This paper analyzes the ratio of tunneling current for channel doping concentration of sub-10 nm asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current in subthreshold region increases in the region of channel length of 10 nm below. Even though asymmetric DGMOSFET is developed to reduce short channel effects, the increase of tunneling current in sub-10 nm is inevitable. As the ratio of tunneling current in off current according to channel doping concentration is calculated in this study, the influence of tunneling current to occur in short channel is investigated. To obtain off current to consist of thermionic emission and tunneling current, the analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for channel doping concentration in sub-10 nm asymmetric DGMOSFET, specially with parameters of channel length, channel thickness, and top/bottom gate oxide thickness and voltage.