• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.31-37
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• 2000

In the case of metal-induced lateral crystallization (MILC) for low temperature poly-Si TFT, offset length between Ni-thin film and the sides of gate could be modified to control the location of MILC boundary. Electrical characteristics were compared to analyze the effect of MILC boundary that was located either in or out of the channel region of the TFT. By removing the MILC boundary from channel region, on current, subthreshold slope and leakage current properties could be improved. When MILC boundary was located in the channel region, leakage current was reduced with electrical stress biasing. The amount of reduction increased as the channel width increased, but it was independent of the channel length.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.789-790
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• 2013

$Er_2O_3/SiO_2$ double-layer gate dielectric shows low gate leakage current and high capacitance. In this paper, we apply $Er_2O_3/SiO_2$ double-layer gate dielectric as a charge trap layer for the first time. $Er_2O_3/SiO_2$ double-layer thickness is optimized by EDISON Nanophysics simulation tools. Using the simulation results, we fabricated Schottky-barrier silicide source/drain transistor, which has10 um/10um gate length and width, respectively. The nonvolatile device demonstrated very promising characterstics with P/E voltage of 11 V/-11 V, P/E speed of 50 ms/500 ms, data retention of ten years, and endurance of $10^4$ P/E cycles.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1939-1947
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• 1999

This paper proposes new line code BIM (Bit Insertion and Manipulation) that is designed to overcome the problems of existing line codes. The block code, one of typical existing line code, has good transmission performance but difficulty in implementation. The other typical existing line code, bit insertion code, is easy to implementation but has bad transmission performance. BIM code in this paper could provide not only good performance but also provides simplicity in the implementation by combining the good points of block code into it of bit insertion code properly. In this paper, 5B6B type BIM code is designed. Designed 5B6B BIM code shows good transmission performance such $\pm$2 DSV, 0 RSD, 7 maximum run length and also it can be implemented under 2000 gates and need only 1 bit redundancy.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4A
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• pp.414-422
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• 2011

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.112-120
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• 2013

In this paper, we propose high-performance H.264/AVC CAVLC encoder for UD video real time processing. Statistical values are obtained in one cycle through the parallel arithmetic and logical operations, using non-zero bit stream which represents zero coefficient or non-zero coefficient. To encode codeword per one cycle, we remove recursive operation in level encoding through parallel comparison for coefficient and escape value. In oder to implement high-speed circuit, proposed CAVLC encoder is designed in two-stage {statical scan, codeword encoding} pipeline. Reducing the encoding table, the arithmetic unit is used to encode non-coefficient and to calculate the codeword. The proposed architecture was simulated in 0.13um standard cell library. The gate count is 33.4Kgates. The architecture can support Ultra Definition Video ($3840{\times}2160$) at 100 frames per second by running at 100MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.257-260
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm“Rijndael”. To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation the round transformation block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.33-43
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into a round transformation block, resulting that two consecutive round functions are simultaneously operated. For area-efficient and low-power implementation, the round transformation block is designed to share the hardware resources for encryption and decryption. An efficient on-the-fly key scheduler is devised to supports the three master-key lengths of 128-b/192-b/256-b, and it generates round keys in the first sub-pipeline stage of each round processing. The Verilog-HDL model of the cryptoprocessor was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}m$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of Sensor Science and Technology
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• v.2 no.1
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• pp.95-99
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• 1993

a-Si : H TFTs for image sensor have been fabricated and their operational characteristics have been investigated. Hydrogenated amorphous silicon nitride(a-SiN : H) films were used for the gate insulator and $n^{+}$-a-Si : H films were depostied for the source and drain contact. The thicknesses of a-SiN : H and a-Si : H films were $2000{\AA}$, respectively and the thickness of $n^{+}$-a-Si : H film was $500{\AA}$. Also the channel length and channel width of a-Si : H TFTs were $50{\mu}m$ and $1000{\mu}m$, respectively. The ON/OFF current ratio, threshold voltage, and field effect mobility of fabricated a-Si : H TFTs were $10^{5}$, 6.3 V, and $0.15cm^{2}/V{\cdot}s$, respectively.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.8
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• pp.116-121
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• 2005

To realize the tap coefficient of a finite impulse response(FIR) filter or the twiddle factor of a fast Fourier transform(FFT) using a current-mode analog circuit, a high accurate current-attenuator circuit is needed This paper introduces an accuracy enhancement technique in the current-mode signal processing. First of all, the DC of set-current error in a conventional current-attenuator using a gate-ratioed orient mirror circuit is analyzed and then, the current-attenuator circuit with a negligibly small DC offset-current error is introduced. The circuit consists of N-output current mirrors connected in parallel with me another. The output current of the circuit is attenuated to 1/N of the input current. On the basis of the Kirchhoff current law, the current scale ratio is determined simply by the number of the current mirrors in the N-current mirrors connected in parallel. In the proposed current-attenuator circuit the scale accuracy is limited by the ac gain error of the current mirror. Considering that a current mirror has a negligibly small ac gain error, the attainable maximum scale accuracy is theoretically -80[dB] to the input current.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.126-126
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• 2010

본 연구에서는 catalyst-free 유기금속 화학증착법 (MOCVD)를 이용하여 사파이어 (0001)면 위에 직접 InN nanorods를 성장하였다. InN 박막의 성장에서 TMIn과 $NH_3$를 전구체로 사용하였으며, 캐리어 가스로는 질소를 사용하였다. 성장 전, 기판에 $1100^{\circ}C$에서 3분간 nitridation 처리를 거친 후 온도를 낮춰 $630{\sim}730^{\circ}C$의 온도범위 에서 InN 박막을 성장하였다. 이때 $710^{\circ}C$의 온도에서 박막은 columnar growth의 특성을 보였으며 동일조건에서 80분간 성장시킨 결과 InN nanorods가 성장되었다. 성장시킨 InN nanorod는 X-선 회절 측정법, 주사 전자 현미경 그리고 투과 전자 현미경을 이용하여 그 특성을 분석하였다. 투과 전자 현미경을 통한 분석결과 지름이 150~200 nm이며 그 길이는 수 ${\mu}m$인 InN nanorod가 성공적으로 성장되었음을 확인하였다. 또한 X-선 회절 측정법과 주사 전자 현미경을 통한 분석에서 이들 nanorods가 대부분 c 방향으로 수직하게 정렬되어 있음을 확인하였다. 또한 Ti/Au (120/80 nm)를 전극으로 사용하여 개개의 nanorod의 전기적 특성을 분석한 결과 linear한 I-V특성이 관찰되었으며 비저항은 평균적으로 $0.0024\;{\Omega}cm$ 이었다. transfer 특성의 측정결과 -50V까지 게이트 전압을 인가하여도 드레인 전류의 변화는 매우 적어 doping level이 상당히 높다고 예상가능하다. 또한 mobility는 $133\;cm^2/Vs$로 도출되었다.