• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.12
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• pp.6047-6052
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• 2013

A cosmetic manufacturing process requires a mold that is inevitable for mass production. Cosmetic containers are one of major factors affecting the customer's purchase decision. In addition, the manufacturing cost in cosmetic container comprises a large portion of the entire product cost. Therefore, a mold satisfying the economical feasibility, aesthetics and functionality is necessary. Among the cosmetic containers, square shape containers have a tendency of having a short shot defect product. The square shaped cosmetic containers are mostly produced as a side gate shape on the two-plate molds. On the other hand, there are two disadvantages, such as gate trace and post processing requirement. The overlap-gateproposed in this study has the characteristics of intaglio gate cutting and no need for post processing. The delivery system of the overlap gate was simulated and compared with the side gate via Moldflow. The improvement in flow, frozen rate, density, and Air trap was confirmed. Based on the simulation results, the mold and performed injection molding was fabricated. In this study, the possibility of the mass production of high aesthetic and functionality cosmetic containers was verified.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.3
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• pp.35-44
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• 2000

세계의 주요 선진국들은 90년대 후반에 디지털 방송을 시작하였으며, 지상파 방송에 대해서 2010년 이내에 대부분 기존의 아날로그 TV 방송을 중단하고 완전히 디지털로 이행하는 계획을 세워 놓고 있다. 디지 털 TV 방송을 시 작함으로써 고화질, 다채널의 이점뿐만 아니라 데이터 방송을 통하여 다양한 부가 데이터 서비스를 제공하는 것이 가능하게 되며, 더 나아가TV를 통한 전자상거래가 가능하게 되는 등 TV수신기는 향후 각 가정의 정보, 오락의 게이트웨이 역할을 할 수 있게 되는 것이 훨씬 더 의미가 있다고 하겠다. 본 고에서는 디지털 방송의 가장 큰 장점으로 대두된 데이터 방송의 세계적인 기술 개발, 표준화 현황 등을 살펴보고 국내 표준화 대응 방향을 검토해 보기로 한다.

• Transactions of the Korean Society of Mechanical Engineers
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• v.19 no.2
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• pp.322-329
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• 1995

Series of experimental work was performed to mold tensile specimens by using the injection molding machine Mold temperature, melt temperature and packing time were chosen as processing parameters for studying the effects of those conditions on the linear shrinkage of final product. Here, each processing variable was decided from the numerical simulation and resin manufacturer's suggested value. The effects of molding conditions on the linear shrinkage in flow direction of the resin were analyzed by measuring the parts 2, 10, 30 and 60 days after molding. As a result, the linear shrinkage increased with the higher mold and melt temperature, and the change of mold temperature has shown more influence. The linear shrinkage of polypropylene has been found to progress up to 30 day with the lapse of the time, and the amount of the linear shrinkage has shown to be between 2.14% and 2.75%. In addition, the effects of packing pressure on the weight has shown to be extremely significant up to freezing time, and proper packing time of the tensile specimen has been found to be 2.0 seconds.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.103-111
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• 2007

In this paper, we propose a VLSI architecture of hardware optimized high quality image signal processor for a Single-chip CMOS Image Sensor(CIS). The Single-chip CIS is usually used for mobile applications, so it has to be implemented as small as possible while maintaining the image quality. Several image processing algorithms are used in ISP to improve captured image quality. Among the several image processing blocks, demosaicing and image filter are the core blocks in ISP. These blocks need line memories, but the number of line memories is limited in a low cost Single-chip CIS. In our design, high quality edge-adaptive and cross channel correlation considered demosaicing algorithm is adopted. To minimize the number of required line memories for image filter, we share the line memories using the characteristics of demosaicing algorithm which consider the cross correlation. Based on the proposed method, we can achieve both high quality and low hardware complexity with a small number of line memories. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 37K, and seven and half line memories are used.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1809-1811
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• 1999

In recent years, attempts have been made to greatly improve the display quality of active-matrix liquid crystal display devices, and many techniques have been proposed to solve such problems as gate delay, feed-through voltage and image sticking. Gate delay is one of the biggest limiting factors for large-screen-size, high-resolution thin-film transistor liquid crystal display (TFT/LCD) design. Many driving method proposed for TFT/LCD progress. Thus we developed gate driving signal generator. Since Pixel-Design Array Simulation Tool (PDAST) can simulate the gate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the driving signals of gate lines on the pixel operations can be effectively analyzed.

• 한국정보통신설비학회:학술대회논문집
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• 2004.08a
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• pp.204-208
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• 2004

인터넷 기술의 발달로 기존의 ADSL망에서 VDSL 및 메트로 이더넷으로 진화함에 따라 PSTN망에 의한 전화서비스가 인터넷폰으로 점차 대체되어가며, 수 Kbps 대역폭의 웹캐스팅서비스는 수 Mbps 고화질 인터넷방송이 가능하며, 이러한 통신과 방송의 융합은 하나의 대세로 간주되어, 케이블 사업자의 케이블 모뎀을 이용한 방송 및 초고속 인터넷 서비스에 이어, 통신사업자들도 VOD 및 IP-TV, 인터넷폰을 동시에 제공하는 방안을 준비중에 있다. KT도 홈게이트웨이 기반의 상용 VOD 서비스가 2004년 6월에 개시되어 TV를 통한 홈엔터테인먼트의 초석을 다지게 되었으며 앞으로 IP-TV 및 인터넷폰 서비스를 계속적으로 제공할 예정에 있다. 본고에서는 통신사업자 측면에서 통신 및 방송서비스가 어떻게 융합될 것이며 최신 이슈가 되고 있는 트리플 플레이 서비스 및 전망 그리고 해외 사례를 알아보고, KT에서 제공중인 IP망관련 서비스에 대하여 살펴보기로 한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.58-65
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.106-111
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the parallel operations and SAD unit control using pattern information, the proposed IME instruction supports not only full search algorithm but also other fast search algorithms. The hardware size is 77K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP runs at 160MHz with sixteen PEGs and it can handle 1080p@30 frame in real time.

• The KIPS Transactions:PartA
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• v.15A no.1
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• pp.61-68
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• 2008

In this paper, we propose the VLSI design of Multi-Format Video Decoder (MFD) to support video codec standards such as MPEG-2, MPEG-4, H.264 and VC-1. The target of the proposed MFD is the Full HD (High Definition) video processing needed for the high-end D-TV SoC (System-on-Chip). The size of the design is reduced by sharing the common large-size resources such as the RISC processor and the on-chip memory among the different codecs. In addition, a detachable architecture is introduced in order to easily add or remove the codecs. The detachable architecture preserves the stability of the previously designed and verified codecs. The size of the design is about 2.4 M gates and the operating clock frequency is 225MHz in the Samsung 65nm process. The proposed MFD supports more than Full-HD (1080p@30fps) video decoding, and the largest number of video codec standards known so far.