• The Bulletin of The Korean Astronomical Society
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• v.46 no.1
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• pp.59.2-59.2
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• 2021

현재 우리나라는 달탐사 개발 사업을 통하여 2022년 8월 발사를 목표로 달 궤도선인 KPLO와 과학임무 및 기술검증 임무를 수행하게 될 임무 탑재체, 임무 수행을 위한 각종 소프트웨어의 개발, 궤도/궤적의 설계 등 일련의 개발 과정을 순조롭게 수행하고 있다. 또한 달 궤도선인 KPLO와 이들 탑재체에 대한 운영과 관제를 수행하는 KPLO 심우주 지상국도 일정에 따라 개발 막바지에 접어들고 있다. 특히 KPLO 심우주 지상국에는 우리나라 대학과 정부출연연구소에 의해서 개발되는 과학탑재체 4기가 달 궤도에서 과학임무를 수행하여 얻게되는 달 탐사 과학자료, 즉, 과학임무자료를 달 탐사에 직접 참여하는 과학자들뿐만 아니라 일반인들도 교육 및 연구에 활용할 수 있도록 달 탐사 과학자료의 저장, 공개, 관리를 위한 Archive system인 KARI Planetary Data System(KPDS)도 함께 개발되고 있다. KPDS는 전문 연구자와 일반인들이 별도의 교육없이 인터넷을 통하여 쉽게 접속하여 KPLO의 과학탑재체가 획득한 달 탐사 과학자료를 검색하여 내려받아 사용할 수 있도록 서비스를 제공할 예정이다. 본 논문에서는 과학탑재체 개발기관 소속의 연구자가 달 탐사 과학자료에 대한 검보정 처리와 과학적 분석을 수행하기 위해서 텔레메트리 형태의 원본형태의 과학자료를 KPDS로부터 다운로드 받는 과정과 검보정 처리가 된 과학자료를 일반 사용자들이 내려 받아 사용할 수 있도록 과학자료가 공개되기까지 일련의 과정을 설명하고, 연구자 및 일반사용자가 직접 접하게 되는 KPDS의 주요한 사용자 환경에 대해서 설명한다.

• Journal of Aerospace System Engineering
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• v.17 no.6
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• pp.127-132
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• 2023

In this study, designing of a Type 4 pressure vessel using the filament winding method was conducted. In order to prevent leakage in consideration of the design of the hydrogen storage tank, a liner was designed by applying high-density polyethylene (HDPE), and the composite structure was designed by stacking carbon/epoxy in the hoop and helical directions. As a theoretical approach, the angle of the helical fiber and fiber thickness of each hoop and helix were designed. The safety of the design was verified using the commercial software ANSYS.

• Annual Conference of KIPS
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• 2008.05a
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• pp.300-303
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• 2008

IT 관련 프로젝트를 진행 시 프로젝트 진행 도중 예상치 못한 많은 문제에 봉착하게 된다. 본 논문에서는 IT 프로젝트 대부분이 도입, 사용하는 요구사항분석-설계-개발-테스트-배포-유지보수단계 중 개발단계 및 유지보수 단계에서 발생할 수 있는 문제점에 초점을 맞추었다. PMG 란 Project Management Negotiator 의 약자로서 개발 시 고객의 요구사항이 변경되면 고객과 개발자 간의 개발에 소요되는 난이도, 일정, 비용에 따른 관점이 다를 수 있으므로, 이러한 차이점을 서로 이해 할 수 있는 범위 내에서 감소시킬 수 있는 모델을 제시한다. 또한 제시한 모델에 근거한 매핑테이블과 프로세스를 개발하고 실제 pilot 시스템을 구축하여 효용성을 검증한다. 제시한 프로젝트 관리 협상 모델을 통하여 일정에 차질 없는 프로젝트가 수행 가능하며 비용절감 및 고객만족 효과를 거둘 수 있다. 결과적으로 일정, 비용 측면 및 고객 만족 세 가지 측면에서 기존의 프로젝트 개발 방법론보다 더 나은 일정준수, 효율성, 정확성 등의 정량적, 정성적 만족을 확보할 수 있다.

• Journal of the Korean Society of Radiology
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• v.82 no.1
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• pp.12-28
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• 2021

Mammography is the primary imaging modality for breast cancer detection; however, a high level of expertise is needed for its interpretation. To overcome this difficulty, artificial intelligence (AI) algorithms for breast cancer detection have recently been investigated. In this review, we describe the characteristics of AI algorithms compared to conventional computer-aided diagnosis software and share our thoughts on the best methods to develop and validate the algorithms. Additionally, several AI algorithms have introduced for triaging screening mammograms, breast density assessment, and prediction of breast cancer risk have been introduced. Finally, we emphasize the need for interest and guidance from radiologists regarding AI research in mammography, considering the possibility that AI will be introduced shortly into clinical practice.

• Journal of IKEEE
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• v.28 no.3
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• pp.432-439
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• 2024

This paper introduces an enhanced Selective Harmonic Elimination (SHE) technique of a single-phase Cascaded H-Bridge (CHB) Multilevel Inverter (MLI) for improving the reliability and power quality of a second life battery energy storage system (ESS). The technique involves solving non-linear transcendental equations derived from Fourier series offline to determine the optimal switching angles for the proposed SHE-PWM implementation. These angles are then applied in real-time via a Look-Up Table (LUT). The Levenberg-Marquardt algorithm, an iterative method, is employed in MATLAB to solve the equations and obtain the switching angles. The effectiveness of the proposed method is validated using PLECS simulation software and is compared with other conventional PWM techniques for MLIs.

• Health Policy and Management
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• v.34 no.2
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• pp.163-177
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• 2024

Background: This study aims to examine changes in fraudulent claim counts and total reimbursements before and after enhancements in counterfeit claim controls and monitoring of provider claim patterns under the "Proactive self-audit pilot program of fraudulent claims." Methods: This study used the claims data and hospital information (July 2021-February 2022) of the Health Insurance Review and Assessment Service. The data was collected from 1,129 hospitals assigned to the pilot program, selected from the providers who filed a claim for reimbursement for intravenous injections. Paired and independent t-tests, along with regression analysis, were utilized to analyze changing patterns and factors influencing claim behaviors. Results: This program led to a reduction in the number of fraudulent claims and the total amount of reimbursements across all levels of hospitals in the experimental groups (except for physicians below 40 years old). In the control group, general hospitals and hospitals demonstrated some significant decreases based on the duration since opening, while clinics showed significant reductions in specified subjects. Additionally, a notable increase was observed among male physicians over the age of 50 years. Overall, claims and reimbursements significantly declined after the intervention. Furthermore, a positive correlation was found between hospital opening duration and claim numbers, suggesting longer-established hospitals were more likely to file claims. Conclusion: The results indicate that the pilot program successfully encouraged providers to autonomously minimize fraudulent claims. Therefore, it is advised to extend further support, including promotional activities, training, seminars, and continuous monitoring, to nonparticipating hospitals to facilitate independent improvements in their claim practices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.107-116
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• 2009

Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nanoelectronic devices which will inherit the throne of CMOS which is the domineering implementation technology for large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors is proposed. After the gate and interconnect structures of. the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit adder, a bit-serial adder, and an ALU bit-slice. For each design, the digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.

• Journal of KIISE:Software and Applications
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• v.31 no.4
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• pp.420-438
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• 2004

Artificially or naturally contained texts in the natural images have significant and detailed information about the scenes. If we develop a method that can extract and recognize those texts in real-time, the method can be applied to many important applications. In this paper, we suggest a new method that extracts the text areas in the natural images using the low-level image features of color continuity. gray-level variation and color valiance and that verifies the extracted candidate regions by using the high-level text feature such as stroke. And the two level features are combined hierarchically. The color continuity is used since most of the characters in the same text lesion have the same color, and the gray-level variation is used since the text strokes are distinctive in their gray-values to the background. Also, the color variance is used since the text strokes are distinctive in their gray-values to the background, and this value is more sensitive than the gray-level variations. The text level stroke features are extracted using a multi-resolution wavelet transforms on the local image areas and the feature vectors are input to a SVM(Support Vector Machine) classifier for the verification. We have tested the proposed method using various kinds of the natural images and have confirmed that the extraction rates are very high even in complex background images.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.62-70
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• 2011

Nowadays image sensor is an essential component in many multimedia devices, and it is covered by a color filter array to filter out specific color components at each pixel. We need a certain algorithm to combine those color components reconstructed a full color image from incomplete color samples output from an image sensor, which is called a demosaicking process. Most existing demosaicking algorithms are developed for ideal image sensors, but they do not work well for the practical cases because of dissimilar characteristics of each sensor. In this paper, we propose a new demosaicking algorithm in which the color filter characteristics are fully utilized to generate a good image. To demonstrate significance of our algorithm, we used a commerically available sensor, CBN385B, which is a sort of Honeycomb-style CFA(Color Filter Array) CCD image sensor. As a performance metric of the algorithm, PSNR(Peak Signal to Noise Ratio) and RGB distribution of the output image are used. We first implemented our algorithm in C-language for simulation on various input images. As a result, we could obtain much enhanced images whose PSNR was improved by 4~8 dB compared to the commonly idealized approaches, and we also could remove the inclined red property which was an unique characteristics of the image sensor(CBN385B).Then we implemented it in hardware to overcome its problem of computational complexity which made it operate slow in software. The hardware was verified on Spartan-3E FPGA(Field Programable Gate Array) to give almost the same performance as software, but in much faster execution time. The total logic gate count is 45K, and it handles 25 image frmaes per second.