• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.108-108
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• 2003

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.921-923
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• 1999

비휘발성 메모리의 고집적화와 적응학습형 뉴럴 소자의 실현을 위하여 1-트랜지스터 구조 강유전체 비휘발성 메모리(MFS-FET)를 SOI 기판위에 제작하고 평가하였다. 먼저 SBT($Sr_{0.8}Bi_{2.2}Ta_{2}O_{9}$)를 직접 Si위에 증착하고 C-V를 측정하여 1V의 메모리 윈도우를 얻음으로써 비휘발성 메모리로써의 동작가능성을 확인하였다. 또한 다양하게 게이트의 W/L 비를 바꾸어서 MFS-FET를 제작하여 다양한 드레인 전압-드레인 전류 특성을 얻었고 실제로 쓰기와 읽기 동작을 수행하여 MFS-FET가 비휘발성 메모리로써 제대로 동작하고 있음을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1033-1044
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• 2002

In this Paper, a new FRAM design technique utilizing grounded-plate PMOS-gate (GPPG) ferroelectric cell is proposed. A GPPG cell consists of a PMOS access transistor and a ferroelectric data storage capacitor. Its plate is grounded. The proposed architecture employs three novel methods for cell operation: 1) $V_{DD}$ -precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the plate control circuitry, it can greatly increase the memory cell efficiency. In addition, differently from other reported common-plate cells, this scheme can supply a sufficient voltage of $V_{DD}$ to the ferroelectric capacitor during detecting and storing the polarization on the cell. Thus, there is no restriction on low voltage operation. Furthermore, by employing a compact column-path circuitry which activates only needed 8-bit data, this architecture can minimize the current consumption of the memory array. A 4- Mb FRAM circuit has been designed with 0.3-um, triple-well/1-polycide/2-metal technology, and the possibility of the realization of GPPG cell architecture has been confirmed.

• The Magazine of the IEIE
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• v.29 no.8
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• pp.976-976
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• 2002

• The Magazine of the IEIE
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• v.29 no.8
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• pp.92-101
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• 2002

• The Magazine of the IEIE
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• v.25 no.7
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• pp.99-106
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• 1998

• Electrical & Electronic Materials
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• v.13 no.4
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• pp.1-15
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• 2000

• Electrical & Electronic Materials
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• v.13 no.4
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• pp.22-26
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• 2000

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.1-8
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• 2005

In this paper, a FRAM design style based on PMOS-gating cell structure is described. The memory cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) $V_{DD}$ precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore, Because this configuration doesn`t need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation for a 2.5-V, 1-Mb FRAM prototype design in a $0.25-{\mu}m$, triple-well technology shows a chip size of $3.22\;mm^{2}$, an access time of 48 ns and an active current of 11 mA. The cell efficiency is 62.52 $\%$. It has gained approximately $20\;\%$ improvement in the cell array efficiency over the conventional plate-driven FRAM scheme.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.3
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• pp.2131-2134
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• 2015

In this study, It has been demonstrated a new and realizable possibility of the ferroelectric random access memory devices by all solution processing method with paper substrates. Organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) thin films were formed on paper substrate with Al electrode for the bottom gate structure using spin-coating technique. Then, they were subjected to annealing process for crystallization. The fabricated PVDF-TrFE thin films were observed by scanning electron microscopy (SEM) and atomic force microscopy (AFM). It was found from polarization versus electric field (P-E) measurement that a PVDF-TrFE thin film on paper substrate showed very good ferroelectric property. This result agree well with that of a PVDF-TrFE thin film fabricated on the rigid Si substrate. It anticipated that these results will lead to the emergence of printable electron devices on paper. Furthermore, it could be fabricated by a solution processing method for ferroelectric random access memory device, which is reliable and very inexpensive, has a high density, and can be also fabricated easily.